# US 2023/0054768 A1 · Differential line driver

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- Number: US 2023/0054768 A1
- Document ID: US20230054768A1
- Status: Published application
- Kind: A1
- Application number: 17/891,054
- Filed: 2022-08-18
- Published: 2023-02-23
- Earliest claimed: 2021-08-19
- Assignees: Pagnanelli Family Trust
- Applicants: Pagnanelli Family Trust
- Inventors: Christopher Pagnanelli
- Web page: https://patentgrep.com/patent/US20230054768A1

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H03K 17/04163: {in field-effect transistor switches}
- H03K 17/08: Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K 17/161: {in field-effect transistor switches}
- H03K 19/0005: {Modifications of input or output impedance}
- H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00)
- H03K 19/018528: {with at least one differential stage}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Provided are, among other things, systems, apparatuses, methods and techniques for driving a differential transmission line and an associated differential load. One such apparatus includes an input data line; an output data line; positive and negative supply rails; a pair of source termination resistors coupled to the positive supply rail; a first pair of n-channel transistors coupled to the source resistors and to the output data line; and a second pair of n-channel transistors coupled to the output line and to the negative supply rail.

## Claims

### Claim 1

An apparatus for driving a differential transmission line and associated differential load, comprising:
a differential input data line;
a differential output data line;
a positive supply rail and a negative supply rail;
a pair of source termination resistors coupled to said positive supply rail;
a first pair of transistors, each having a first terminal coupled to said differential input data line, a second terminal coupled to said negative supply rail, and a third terminal coupled to said output data line;
a second pair of transistors, each having a first terminal coupled to said differential input data line, a second terminal coupled to said output data line, and a third terminal coupled to one of said source termination resistors,
wherein each of said source termination resistors has an impedance that is approximately equal to the characteristic impedance of the differential transmission line and to the impedance of the associated differential load, and
wherein each transistor within said first pair of transistors and said second pair of transistors is a n-channel device.

### Claim 2 (depends on 1)

An apparatus according to claim 1, wherein at least one of the transistors from among said first pair of transistors and said second pair of transistors is a field-effect transistor.

### Claim 3 (depends on 1)

An apparatus according to claim 1, wherein at least one of the transistors from among said first pair of transistors and said second pair of transistors is a bipolar-junction transistor.

### Claim 4 (depends on 1)

An apparatus according to claim 1, wherein the negative supply rail is at ground potential.

### Claim 5 (depends on 1)

An apparatus according to claim 1, wherein each of said source termination resistors has an impedance that is within ±10% of the characteristic impedance of the differential transmission line and of the impedance of the associated differential load.

### Claim 6 (depends on 1)

An apparatus according to claim 1, wherein the third terminal of each of the second pair of transistors is coupled to said positive supply rail through one of said source termination resistors.

### Claim 7 (depends on 1)

An apparatus according to claim 1, wherein the second terminal of each transistor in the second pair of transistors is directly connected to the third terminal of one of the transistors in the first pair of transistors.

### Claim 8 (depends on 1)

An apparatus according to claim 1, wherein the transistors are sized such that the transistors that are turned on cumulatively provide a voltage drop of less than ¼ the voltage potential across the positive and negative supply rails when an intended drive level is applied at said differential input data line.

### Claim 9 (depends on 1)

An apparatus according to claim 1, wherein the transistors are sized such that the transistors that are turned on cumulatively provide a voltage drop of less than ¼ the voltage potential across the positive and negative supply rails when an intended current passes through said differential output data line.

### Claim 10 (depends on 1)

An apparatus according to claim 1, wherein the first terminal of each transistor of the first pair of transistors and the second pair of transistors is a control terminal for said transistor.

### Claim 11 (depends on 10)

An apparatus according to claim 10, wherein the differential input data line includes a first data line and a second data line, and wherein each of the first pair of transistors and the second pair of transistors includes one transistor having its control terminal coupled to the first data line and another transistor having its control terminal coupled to the second data line.