# US 2023/0054719 A1 · Gallium nitride (gan) layer transfer and regrowth for integrated circuit technology

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- Number: US 2023/0054719 A1
- Document ID: US20230054719A1
- Status: Published application
- Kind: A1
- Application number: 17/408,025
- Filed: 2021-08-20
- Published: 2023-02-23
- Earliest claimed: 2021-08-20
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Pratik KOIRALA; Souvik GHOSH; Paul NORDEEN; Tushar TALUKDAR; Thomas HOFF; Ibrahim BAN; Kimin JUN; Samuel James BADER; Marko RADOSAVLJEVIC; Nicole K. THOMAS; Paul B. FISCHER; Han Wui THEN
- Web page: https://patentgrep.com/patent/US20230054719A1

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/111: {Field plates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a substrate;
an insulator layer over the substrate; and
a device layer directly on the insulator layer, the device layer comprising gallium and nitrogen and having an uppermost face consisting of gallium, and the device layer having a thickness of less than approximately 500 nanometers.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the device layer is a Ga-polar GaN layer.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the insulator layer comprises silicon and oxygen.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, further comprising a high voltage GaN device on the device layer.

### Claim 5 (depends on 4)

The integrated circuit structure of claim 4, wherein the high voltage GaN device comprises:
a plurality of gate structures over the device layer;
a source region on a first side of the plurality of gate structures;
a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and
a drain field plate above the drain region wherein the drain field plate is coupled to the source region.

### Claim 6

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a substrate;
an insulator layer over the substrate; and
a device layer directly on the insulator layer, the device layer comprising gallium and nitrogen and having an uppermost face consisting of gallium, and the device layer having a thickness of less than approximately 500 nanometers.

### Claim 7 (depends on 6)

The computing device of claim 6, further comprising:
a memory coupled to the board.

### Claim 8 (depends on 6)

The computing device of claim 6, further comprising:
a communication chip coupled to the board.

### Claim 9 (depends on 6)

The computing device of claim 6, further comprising:
a camera coupled to the board.

### Claim 10 (depends on 6)

The computing device of claim 6, wherein the component is a packaged integrated circuit die.

### Claim 11

An integrated circuit structure, comprising:
a substrate;
an insulator layer over the substrate; and
a device layer directly on the insulator layer, the device layer comprising gallium and nitrogen and having an uppermost face consisting of nitrogen, and the device layer having a thickness of less than approximately 500 nanometers.

### Claim 12 (depends on 11)

The integrated circuit structure of claim 11, wherein the device layer is an N-polar GaN layer.

### Claim 13 (depends on 11)

The integrated circuit structure of claim 11, wherein the insulator layer comprises silicon and oxygen.

### Claim 14 (depends on 11)

The integrated circuit structure of claim 11, further comprising a high voltage GaN device on the device layer.

### Claim 15 (depends on 14)

The integrated circuit structure of claim 14, wherein the high voltage GaN device comprises:
a plurality of gate structures over the device layer;
a source region on a first side of the plurality of gate structures;
a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and
a drain field plate above the drain region wherein the drain field plate is coupled to the source region.

### Claim 16

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a substrate;
an insulator layer over the substrate; and
a device layer directly on the insulator layer, the device layer comprising gallium and nitrogen and having an uppermost face consisting of nitrogen, and the device layer having a thickness of less than approximately 500 nanometers.

### Claim 17 (depends on 16)

The computing device of claim 16, further comprising:
a memory coupled to the board.

### Claim 18 (depends on 16)

The computing device of claim 16, further comprising:
a communication chip coupled to the board.

### Claim 19 (depends on 16)

The computing device of claim 16, further comprising:
a camera coupled to the board.

### Claim 20 (depends on 16)

The computing device of claim 16, wherein the component is a packaged integrated circuit die.