# US 2023/0054524 A1 · Video processing apparatus using internal prediction buffer that is shared by multiple coding tools for prediction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0054524 A1 - Document ID: US20230054524A1 - Status: Published application - Kind: A1 - Application number: 17/678,045 - Filed: 2022-02-23 - Published: 2023-02-23 - Earliest claimed: 2021-08-17 - Assignees: Mediatek Inc. - Applicants: Mediatek Inc. - Inventors: Chih-Wen Yang; Chi-Hung Chen; Kai-Chun Lin; Chien-Wei Lin; Meng-Jye Hu - Web page: https://patentgrep.com/patent/US20230054524A1 ## CPC - H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence) - H04N 19/105: Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction - H04N 19/127: Prioritisation of hardware or computational resources - H04N 19/15: by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer - H04N 19/156: Availability of hardware or computational resources, e.g. encoding based on power-saving criteria - H04N 19/157: Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter - H04N 19/172: the region being a picture, frame or field - H04N 19/503: involving temporal prediction (adaptive coding with adaptive selection between spatial and temporal predictive coding H04N19/107; adaptive coding with adaptive selection among a plurality of temporal predictive coding modes H04N19/109) - H04N 19/593: involving spatial prediction techniques - H04N 19/85: using pre-processing or post-processing specially adapted for video compression - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data. ## Claims ### Claim 1 A video processing apparatus implemented in a chip, comprising: an on-chip prediction buffer, shared by a plurality of coding tools for prediction, and arranged to store reference data; and a processing circuit, arranged to support the plurality of coding tools for prediction, read a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the plurality of coding tools and enabled by the processing circuit, and write output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data. ### Claim 2 (depends on 1) The video processing apparatus of claim 1, wherein the plurality of coding tools further comprise a second coding tool; and the plurality of first reference data stored in the on-chip prediction buffer are used by the first coding tool enabled by the processing circuit, and are reused by the second coding tool enabled by the processing circuit. ### Claim 3 (depends on 1) The video processing apparatus of claim 1, wherein any reference data required by the plurality of coding tools is only read from the on-chip prediction buffer by the processing circuit. ### Claim 4 (depends on 1) The video processing apparatus of claim 1, wherein the plurality of coding tools comprise a plurality of intra prediction tools. ### Claim 5 (depends on 4) The video processing apparatus of claim 4, wherein the plurality of intra prediction tools comprise at least two of intra block copy (IBC), combined inter intra prediction (CIIP), cross-component linear model (CCLM), and multiple reference line prediction (MRLP). ### Claim 6 (depends on 1) The video processing apparatus of claim 1, wherein the reference data stored in the on-chip prediction buffer comprise prediction data and reconstructed data. ### Claim 7 (depends on 1) The video processing apparatus of claim 1, wherein the reference data stored in the on-chip prediction buffer comprise intra prediction data and inter prediction data. ### Claim 8 (depends on 1) The video processing apparatus of claim 1, wherein the reference data stored in the on-chip prediction buffer comprise intra reconstructed data and inter reconstructed data. ### Claim 9 (depends on 1) The video processing apparatus of claim 1, wherein the reference data stored in the on-chip prediction buffer comprise reconstructed data, the video processing apparatus is coupled to an off-chip memory, the on-chip prediction buffer is further arranged to output the reconstructed data to the off-chip memory, and the video processing apparatus further comprises: a post-processing circuit, arranged to apply post-processing to reconstructed data read from the off-chip memory, wherein the post-processing circuit does not apply post-processing to any reconstructed data of a frame until all reconstructed data of the frame are available in the off-chip memory. ### Claim 10 (depends on 1) The video processing apparatus of claim 1, wherein the reference data stored in the on-chip prediction buffer comprise reconstructed data, and the video processing apparatus further comprises: a post-processing circuit, arranged to apply post-processing to reconstructed data read from the on-chip prediction buffer, wherein the post-processing circuit starts to apply post-processing to reconstructed data of a frame before all reconstructed data of the frame are generated from the processing circuit. ### Claim 11 A video processing apparatus comprising: a prediction buffer, shared by a plurality of coding tools for prediction, and arranged to store reference data, wherein the prediction buffer is not a dynamic random access memory (DRAM); and a processing circuit, arranged to support the plurality of coding tools for prediction, read a plurality of first reference data from the prediction buffer as input data of a first coding tool that is included in the plurality of coding tools and enabled by the processing circuit, and write output data of the first coding tool enabled by the processing circuit into the prediction buffer as a plurality of second reference data. ### Claim 12 (depends on 11) The video processing apparatus of claim 11, wherein the plurality of coding tools further comprise a second coding tool; and the plurality of first reference data stored in the prediction buffer are used by the first coding tool enabled by the processing circuit, and are reused by the second coding tool enabled by the processing circuit. ### Claim 13 (depends on 11) The video processing apparatus of claim 11, wherein any reference data required by the plurality of coding tools is only read from the prediction buffer by the processing circuit. ### Claim 14 (depends on 11) The video processing apparatus of claim 11, wherein the plurality of coding tools comprise a plurality of intra prediction tools. ### Claim 15 (depends on 14) The video processing apparatus of claim 14, wherein the plurality of intra prediction tools comprise at least two of intra block copy (IBC), combined inter intra prediction (CIIP), cross-component linear model (CCLM), and multiple reference line prediction (MRLP). ### Claim 16 (depends on 11) The video processing apparatus of claim 11, wherein the reference data stored in the prediction buffer comprise prediction data and reconstructed data. ### Claim 17 (depends on 11) The video processing apparatus of claim 11, wherein the reference data stored in the prediction buffer comprise intra prediction data and inter prediction data. ### Claim 18 (depends on 11) The video processing apparatus of claim 11, wherein the reference data stored in the prediction buffer comprise intra reconstructed data and inter reconstructed data. ### Claim 19 (depends on 11) The video processing apparatus of claim 11, wherein the reference data stored in the prediction buffer comprise reconstructed data, the video processing apparatus is coupled to the DRAM, the prediction buffer is further arranged to output the reconstructed data to the DRAM, and the video processing apparatus further comprises: a post-processing circuit, arranged to apply post-processing to reconstructed data read from the DRAM, wherein the post-processing circuit does not apply post-processing to any reconstructed data of a frame until all reconstructed data of the frame are available in the DRAM. ### Claim 20 (depends on 11) The video processing apparatus of claim 11, wherein the reference data stored in the prediction buffer comprise reconstructed data, and the video processing apparatus further comprises: a post-processing circuit, arranged to apply post-processing to reconstructed data read from the prediction buffer, wherein the post-processing circuit starts to apply post-processing to reconstructed data of a frame before all reconstructed data of the frame are generated from the processing circuit.