# US 2023/0054054 A1 · Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0054054 A1 - Document ID: US20230054054A1 - Status: Published application - Kind: A1 - Application number: 17/409,355 - Filed: 2021-08-23 - Published: 2023-02-23 - Earliest claimed: 2021-08-23 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Alyssa N. Scarbrough; John D. Hopkins; Jordan D. Greenlee - Web page: https://patentgrep.com/patent/US20230054054A1 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. The insulative tier immediately-above a lowest of the conductive tiers comprises a lower first insulating material and an upper second insulating material above the upper first insulating material. The upper second insulating material is of different composition from that of the lower first insulating material. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed. ## Claims ### Claim 1 A method used in forming a memory array comprising strings of memory cells, comprising: forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, the lower portion comprising lower first insulating material; forming sacrificial rails in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions and extend through the lower first insulating material; forming upper second insulating material directly above the lower first insulating material and directly above the sacrificial rails, the upper second insulating material being of different composition from that of the lower first insulating material; forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the upper second insulating material and above the sacrificial rails, and forming channel-material strings that extend through the upper portion to the lower portion; forming horizontally-elongated trenches into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend through the upper portion and through the upper second insulating material to the sacrificial rail immediately-therebelow; and removing the sacrificial rails through the trenches. ### Claim 2 (depends on 1) The method of claim 1 wherein the upper second insulating material is formed directly against the lower first insulating material. ### Claim 3 (depends on 1) The method of claim 1 wherein the upper second insulating material is formed directly against the sacrificial rails. M122-7937 — M01.docx 2 of 12 ### Claim 4 (depends on 1) The method of claim 1 wherein, the upper second insulating material is formed directly against the lower first insulating material; and the upper second insulating material is formed directly against the sacrificial rails. ### Claim 5 (depends on 1) The method of claim 1 wherein the lower first insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 6 (depends on 1) The method of claim 1 wherein the upper second insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 7 (depends on 1) The method of claim 1 wherein each of the lower first insulating material and the upper second insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 8 (depends on 1) The method of claim 1 wherein only one of the lower first insulating material and the upper second insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 9 (depends on 1) The method of claim 1 wherein, the lower portion is formed above a conductor tier comprising conductor material; the lower portion comprises a lowest of the first tiers comprising sacrificial material; the channel-material strings extending to the lowest first tier in the lower portion; after removing the sacrificial rails, isotropically etching the exposed sacrificial material from the lowest first tier through the trenches; and after the isotropically etching, forming conductive material in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. ### Claim 10 (depends on 9) The method of claim 9 comprising: silicon dioxide laterally-outward of the channel-material strings; and after the isotropically etching of the exposed sacrificial material from the lowest first tier and before forming the conductive material, isotropically etching the silicon dioxide selectively relative to any exposed of the lower first insulating material and any exposed of the upper second insulating material. ### Claim 11 (depends on 10) The method of claim 10 wherein at least one of the lower first insulating material and the upper second insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 12 (depends on 11) The method of claim 11 wherein each of the lower first insulating material and the upper second insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 13 A method used in forming a memory array comprising strings of memory cells, comprising: forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, the lower portion comprising lower first insulating material; forming sacrificial rails in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the lower first insulating material; forming upper second insulating material directly above the lower first insulating material and directly above the sacrificial rails, the upper second insulating material comprising a same composition as that of the lower first insulating material, the same composition being other than undoped stoichiometric silicon dioxide and other than stoichiometric silicon nitride; forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the upper second insulating material and above the sacrificial rails, and forming channel-material strings that extend through the upper portion to the lower portion; forming horizontally-elongated trenches into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend through the upper portion and through the upper second insulating material to the sacrificial rail immediately-therebelow; and removing the sacrificial rails through the trenches. ### Claim 14 (depends on 13) The method of claim 13 wherein the same composition comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 15 (depends on 13) The method of claim 13 wherein, the lower portion is formed above a conductor tier comprising conductor material; the lower portion comprises a lowest of the first tiers comprising sacrificial material; the channel-material strings extending to the lowest first tier in the lower portion; after removing the sacrificial rails, isotropically etching the exposed sacrificial material from the lowest first tier through the trenches; and after the isotropically etching, forming conductive material in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. ### Claim 16 (depends on 15) The method of claim 15 comprising: silicon dioxide laterally-outward of the channel-material strings; and after the isotropically etching of the exposed sacrificial material from the lowest first tier and before forming the conductive material, isotropically etching the silicon dioxide selectively relative to any exposed of the same composition material. ### Claim 17 (depends on 16) The method of claim 16 wherein the same composition comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 18 A method used in forming a memory array comprising strings of memory cells, comprising: forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, the lower portion comprising sacrificial rails that are individually between immediately-laterally-adjacent of the memory-block regions; forming insulating material aside and directly above the sacrificial rails, the insulating material comprising material other than undoped stoichiometric silicon dioxide and other than stoichiometric silicon nitride; forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the insulating material and above the sacrificial rails, and forming channel-material strings that extend through the upper portion to the lower portion; forming horizontally-elongated trenches into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend through the upper portion and through the insulating material to the sacrificial rail immediately-therebelow; and removing the sacrificial rails through the trenches. ### Claim 19 (depends on 18) The method of claim 18 wherein the insulating material is formed directly against the sacrificial rails. ### Claim 20 (depends on 18) The method of claim 18 wherein the insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 21 (depends on 18) The method of claim 18 wherein, the lower portion is formed above a conductor tier comprising conductor material; the lower portion comprises a lowest of the first tiers comprising sacrificial material; the channel-material strings extending to the lowest first tier in the lower portion; after removing the sacrificial rails, isotropically etching the exposed sacrificial material from the lowest first tier through the trenches; and after the isotropically etching, forming conductive material in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. ### Claim 22 (depends on 21) The method of claim 21 comprising: silicon dioxide laterally-outward of the channel-material strings; and after the isotropically etching of the exposed sacrificial material from the lowest first tier and before forming the conductive material, isotropically etching the silicon dioxide selectively relative to any exposed of the insulating material. ### Claim 23 (depends on 22) The method of claim 22 wherein the isotropically etching of the silicon dioxide is conducted selectively relative to any exposed of the insulating material. ### Claim 24 (depends on 22) The method of claim 22 wherein the insulating material comprises at least one of carbon-doped silicon dioxide, boron-doped silicon dioxide, hafnium oxide, silicon oxynitride, and silicon carbide. ### Claim 25 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the channel-material strings directly electrically coupling to conductor material of the conductor tier; the insulative tier immediately-above a lowest of the conductive tiers comprising a lower first insulating material and an upper second insulating material above the upper first insulating material, the upper second insulating material being of different composition from that of the lower first insulating material; and intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. ### Claim at position 26 26-37. (canceled) ### Claim 38 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the channel-material strings directly electrically coupling to conductor material of the conductor tier; the insulative tier immediately-above a lowest of the conductive tiers comprising a lower first insulating material and an upper second insulating material above the upper first insulating material, the upper second insulating material comprising a same composition as that of the lower first insulating material, the same composition being other than undoped stoichiometric silicon dioxide and other than stoichiometric silicon nitride; and intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. ### Claim at position 28 39-44. (canceled) ### Claim 45 A memory array comprising strings of memory cells, comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the channel-material strings directly electrically coupling to conductor material of the conductor tier; the insulative tier immediately-above a lowest of the conductive tiers comprising insulating material comprising material other than undoped stoichiometric silicon dioxide and other than stoichiometric silicon nitride; and intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. ### Claim at position 30 46-51. (canceled)