# US 2023/0054034 A1 · 3d package for semiconductor thermal management

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2023/0054034 A1
- Document ID: US20230054034A1
- Status: Published application
- Kind: A1
- Application number: 17/408,708
- Filed: 2021-08-23
- Published: 2023-02-23
- Earliest claimed: 2021-08-23
- Assignees: Palo Alto Research Center Incorporated
- Applicants: Palo Alto Research Center Incorporated
- Inventors: Christopher Chua; Joerg Martini; Mark Teepe; Yu Wang; Qian Wang
- Web page: https://patentgrep.com/patent/US20230054034A1

## CPC

- B41J 2/455: using laser arrays {, the laser array being smaller than the medium to be recorded}
- B41J 2/45: using light-emitting diode {[LED] or laser} arrays
- B41J 2/451: {Special optical means therefor, e.g. lenses, mirrors, focusing means}
- H01S 5/02315: Support members, e.g. bases or carriers
- H01S 5/02326: Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
- H01S 5/0233: Mounting configuration of laser chips
- H01S 5/0239: Combinations of electrical or optical elements
- H01S 5/02423: {Liquid cooling, e.g. a liquid cools a mount of the laser}
- H01S 5/183: having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S 5/4012: {Beam combining, e.g. by the use of fibres, gratings, polarisers, prisms}
- H01S 5/4018: {Lasers electrically in series}
- H01S 5/4025: {Array arrangements, e.g. constituted by discrete laser diodes or laser bar (H01S5/42 takes precedence)}
- H01S 5/423: {having a vertical cavity}
- H01S 5/02438: {Characterized by cooling of elements other than the laser chip, e.g. an optical element being part of an external cavity or a collimating lens}
- B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL

## Abstract

A 3D package for semiconductor thermal management can include a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel. Integrated slots can be provided for accepting and mounting semiconductor components. Mounting holes can be formed in the mechanical block for securing optical elements. At least one semiconductor laser array die can be secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel.

## Claims

### Claim 1

A 3D package for semiconductor thermal management, comprising:
a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel;
integrated slots for accepting and mounting semiconductor components;
mounting holes formed therein for securing optical elements; and
at least one semiconductor laser array die secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel.

### Claim 2 (depends on 1)

The 3D package of claim 1, further comprising at least one driver electronic circuit integrated on the 3D submount.

### Claim 3 (depends on 2)

The 3D package of claim 2, wherein the at least one driver electronic circuit is a PCB incorporating driver electronics.

### Claim 4 (depends on 2)

The 3D package of claim 2, wherein the at least one driver electronic circuit is an Application-Specific Integrated Circuit (ASIC).

### Claim 5 (depends on 2)

The 3D package of claim 2, further comprising at least one interposer configured to adopt the electrical contact pad layout of pixels in the at least one semiconductor laser array die to an electrical contact pad layout of the at least one driver electronic circuit.

### Claim 6 (depends on 1)

The 3D package of claim 1, further comprising a plurality of wirebonds adapted for connection to at least one of: an external driver system, an interposer, and contact pads of driver electronics bypassing interposers.

### Claim 7 (depends on 1)

The 3D package of claim 1, further comprising optical elements secured to the mounting holes formed optically coupled to the semiconductor laser array

### Claim 8 (depends on 1)

The 3D package of claim 1, wherein the at least one semiconductor laser array die further comprises a plurality of independently addressable pixels arranged in a linear array on a common substrate chip, wherein each pixel further comprises one or more surface-emitting laser apertures utilizing a common cathode and a dedicated channel associated with an address trace line for each pixel.

### Claim 9 (depends on 8)

The 3D package of claim 8, wherein a power level of each pixel is about 50 mW and requires thermal management.

### Claim 10 (depends on 1)

The 3D package of claim 1, wherein the at least one semiconductor laser array die secured to the 3D mechanical block is directly die attached to the 3D mechanical block with an electrical and thermal interface.

### Claim 11

A 3D package for semiconductor thermal management as part of a printing system, comprising:
a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel;
integrated slots for accepting and mounting semiconductor components;
at least one semiconductor laser array die secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel; and
mounting holes formed in the mechanical block for securing a lens array aligned with the semiconductor array to produce imaging with light from pixels of the at least one semiconductor laser array die onto a blanket cylinder associated with the printing system.

### Claim 12 (depends on 11)

The 3D package of claim 11, wherein the 3D mechanical block further comprises a vapor extraction unit mounted to a vapor extraction mount coupled to the 3D mechanical block and placed close to a focus area of the lens array, wherein the vapor extraction unit extracts fountain solution vapor generated by selective laser heating from the plurality of independently addressable surface emitting lasers.

### Claim 13 (depends on 11)

The 3D package of claim 11, wherein the semiconductor laser array further comprises a plurality of independently addressable surface emitting lasers arranged in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each laser of the plurality of independently addressable pixels of the surface emitting laser array operating at power level reaching 50 mW and requiring thermal management.

### Claim 14 (depends on 11)

The 3D package of claim 11, wherein at least one semiconductor laser array die secured to the 3D mechanical block is directly die attached with an electrical and thermal interface.

### Claim 15 (depends on 11)

The 3D package of claim 11, wherein at least one semiconductor laser array die directly attached by a die to the 3D mechanical block comprises a vertical cavity surface emitting laser array.

### Claim 16 (depends on 15)

The 3D package of claim 15, wherein the at least one semiconductor laser array die further comprises a plurality of independently addressable surface emitting lasers arranged in a linear array on a common substrate chip and including a common anode and a dedicated channel associated with an address trace line for each laser of the plurality of independently addressable surface emitting lasers operating at power level reaching 50 mW and requiring thermal management.

### Claim 17

A 3D package for semiconductor thermal management as part of a printing system, comprising:
a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel;
integrated slots for accepting and mounting semiconductor components;
at least one semiconductor laser array die secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel;
mounting holes formed in the mechanical block for securing a lens array aligned with the semiconductor array to produce imaging with light from pixels of the at least one semiconductor laser array die onto a blanket cylinder associated with the printing system; and
a vapor extraction unit mounted to a vapor extraction mount coupled to the 3D mechanical block and placed close to a focus area of the lens array, wherein the vapor extraction unit extracts fountain solution vapor generated by selective laser heating from the plurality of independently addressable surface emitting lasers.

### Claim 18 (depends on 17)

The 3D package of claim 17, wherein the at least one semiconductor laser array die further comprises a plurality of independently addressable surface emitting lasers arranged in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each laser of the plurality of independently addressable surface emitting lasers operating at power level reaching 50 mW and requiring thermal management.

### Claim 19 (depends on 18)

The 3D package of claim 18, wherein each independently addressable semiconductor laser further comprises more than one aperture operable in common with its associated address trace line to attain a larger effective aperture size, and wherein each of the more than one apertures of the plurality of surface emitting lasers further comprises a non-symmetric aperture shape configured to fit within a pitch of each address trace line associated with each channel for each of the plurality of independently addressable surface emitting lasers.

### Claim 20 (depends on 19)

The 3D package of claim 19, wherein the more than one aperture operable in common to attain a larger effective aperture size is a double-aperture pixel.

### Claim 21 (depends on 19)

The 3D package of claim 19, wherein the more than one aperture operable in common to attain a larger effective aperture size is a triple-aperture pixel.

### Claim 22 (depends on 19)

The 3D package of claim 19, wherein address trace lines associated with each of the plurality of independently addressable surface emitting lasers are fabricated to be at no more than a 22 micrometer pitch with respect to each other.

### Claim 23 (depends on 19)

The 3D package ay of claim 19, wherein address trace lines are fabricated at a width that allows low sheet resistance and negligible voltage drops when electrified with a signal during operation of the semiconductor laser array.

### Claim 24 (depends on 19)

The 3D package of claim 19, further comprising an electrical contact pad associated with each address trace line for each independently addressable semiconductor laser, wherein each electrical contact pad is configured to accept wire bonding.

### Claim 25 (depends on 19)

The 3D package of claim 19, wherein the plurality of independently addressable surface emitting lasers are arranged along two rows with one set of address lines coming in from a top of the common substrate chip and are connecting to a first row of independently addressable surface emitting lasers and another set of address lines coming in from the bottom of the common substrate chip and are connecting to a second row of independently addressable surface emitting lasers.

### Claim 26 (depends on 25)

The 3D package of claim 25, further comprising a driver circuit attached to each of the top row and bottom row of by the wire bonding to the electrical pads associated with each of the top row and bottom row.

### Claim 27 (depends on 25)

The 3D package ay of claim 25, wherein the first and second rows are offset with respect to each other to form an interdigitated linear array of light emitters on nor more than a 22 micrometer pitch.

### Claim 28 (depends on 25)

The 3D package of claim 25, wherein the common substrate chip is fabricated at 21 mm long by 2 mm wide can contain at least 1000 independently addressable surface emitting lasers thereon.

### Claim 29 (depends on 28)

The 3D package of claim 28, further comprising more than one common substrate chip tiled and stitched together side-by-side to provide an at least 11-inch wide, 1200 pdi imager.

### Claim 30 (depends on 28)

The 3D package of claim 28, further comprising more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200 pdi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.