# US 2023/0054020 A1 · Semiconductor package and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0054020 A1 - Document ID: US20230054020A1 - Status: Published application - Kind: A1 - Application number: 17/981,465 - Filed: 2022-11-06 - Published: 2023-02-23 - Earliest claimed: 2020-03-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Wei-Chih Lai; Chien-Chia Chiu; Chen-Hua Yu; Der-Chyang Yeh; Cheng-Hsien Hsieh; Li-Han Hsu; Tsung-Shu Lin; Wei-Cheng Wu; Yu-Chen Hsu - Web page: https://patentgrep.com/patent/US20230054020A1 ## CPC - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/685: comprising multiple insulating layers - H10W 72/071: {Connecting or disconnecting} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/63: Vias, e.g. via plugs - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. ## Claims ### Claim 1 A semiconductor package, comprising: a circuit substrate; semiconductor dies, disposed on the circuit substrate and electrically connected with the circuit substrate, wherein the semiconductor dies are arranged as a column, and the semiconductor dies are spaced apart with a gap between two most adjacent semiconductor dies; a beam structure, disposed on the circuit substrate and located beside the column of the semiconductor dies; a heat sink lid, disposed over the semiconductor dies and on the beam structure; and a joining material disposed between the heat sink lid and the semiconductor dies, wherein a through opening that extends through the heat sink lid and the joining material in a thickness direction exposes a portion of the beam structure and the gap between the two most adjacent semiconductor dies. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the through opening extends in a first direction substantially parallel to an extending direction of the gap with a first extending length, and the first extending length is smaller than a length of the heat sink lid in the first direction. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the through opening extends in a first direction substantially parallel to an extending direction of the gap with a first extending length, and the first extending length is substantially equivalent to a length of the heat sink lid in the first direction. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the heat sink lid is divided into two pieces by the through opening. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein a spreading span of the heat sink lid is smaller than an area of the circuit substrate. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein a spreading span of the heat sink lid is substantially the same as an area of the circuit substrate. ### Claim 7 (depends on 1) The semiconductor package of claim 1, further comprising a ring wall disposed on the circuit substrate and surrounding the semiconductor dies and the beam structure. ### Claim 8 (depends on 7) The semiconductor package of claim 7, wherein the heat sink lid fully covers the ring wall. ### Claim 9 (depends on 7) The semiconductor package of claim 7, wherein the heat sink lid covers the semiconductor dies and partially covers the beam structure without covering the ring wall. ### Claim 10 A semiconductor package, comprising: a circuit substrate; first semiconductor dies, disposed on the circuit substrate and electrically connected with the circuit substrate, wherein the first semiconductor dies are disposed side by side and laterally wrapped by an encapsulant, and the first semiconductor dies are spaced apart with a portion of the encapsulant filled between two most adjacent first semiconductor dies; second semiconductor dies, disposed on the circuit substrate, located beside the first semiconductor dies and electrically connected with the circuit substrate, wherein the second semiconductor dies are disposed side by side and spaced apart with a gap between two most adjacent second semiconductor dies; a frame structure, disposed on the circuit substrate, wherein the frame structure includes a ring portion enclosing the first semiconductor dies and the second semiconductor dies, and a beam portion disposed between the first semiconductor dies and the second semiconductor dies; a heat sink lid, disposed over the first semiconductor dies and the second semiconductor dies and on the frame structure; and a bonding material disposed between the heat sink lid and the first semiconductor dies and the second semiconductor dies, wherein an open slit that extends through the heat sink lid and the bonding material in a thickness direction exposes the portion of the encapsulant and exposes the gap between the two most adjacent second semiconductor dies. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the beam portion is connected to the ring portion at both ends of the beam portion. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the open slit extends in a first direction perpendicular to an extending direction of the beam portion, and the open slit exposes a portion of the beam portion and portions of the ring portion. ### Claim 13 (depends on 11) The semiconductor package of claim 11, wherein the open slit extends in a first direction perpendicular to an extending direction of the beam portion, and the open slit exposes a portion of the beam portion. ### Claim 14 (depends on 11) The semiconductor package of claim 11, wherein the heat sink lid includes a cap disposed over the frame structure and extending substantially parallel to the circuit substrate, a ridge portion extending across the cap and protruded from the cap and a rim at a periphery of the cap, a location of the ridge portion corresponds to a location of the beam portion of the frame structure, and a location of the rim corresponds to a location of the ring portion of the frame structure. ### Claim 15 (depends on 11) The semiconductor package of claim 11, wherein the heat sink lid includes a cap disposed over the frame structure and extending substantially parallel to the circuit substrate and a ridge portion extending across the cap and protruded from the cap, and a location of the ridge portion corresponds to a location of the beam portion of the frame structure. ### Claim 16 (depends on 10) The semiconductor package of claim 10, further comprising passive components located on the circuit substrate and located beside the first and second semiconductor dies, wherein the passive components are electrically connected to the circuit substrate. ### Claim 17 A manufacturing method of a semiconductor package, comprising: providing a circuit substrate; mounting semiconductor dies on the circuit substrate; bonding the semiconductor dies to the circuit substrate, wherein the semiconductor dies are spaced apart with a gap between two most adjacent semiconductor dies; attaching a beam structure to the circuit substrate beside the semiconductor dies; applying a joining material onto the semiconductor dies without covering the gap; and attaching a heat sink lid on the joining material and the semiconductor dies and on the beam structure without covering the gap, wherein a through opening extending through the heat sink lid and the joining material in a thickness direction is formed exposing a portion of the beam portion and the gap. ### Claim 18 (depends on 17) The manufacturing method of claim 17, further comprising laterally wrapping the semiconductor dies with an encapsulant that fills up the gap. ### Claim 19 (depends on 17) The manufacturing method of claim 17, further comprising attaching a ring wall on the circuit substrate surrounding the semiconductor dies and the beam structure. ### Claim 20 (depends on 17) The manufacturing method of claim 17, further comprising mounting passive components on the circuit substrate and beside the semiconductor dies.