# US 2023/0053981 A1 · Inferring future value for speculative branch resolution > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0053981 A1 - Document ID: US20230053981A1 - Status: Published application - Kind: A1 - Application number: 17/406,186 - Filed: 2021-08-19 - Published: 2023-02-23 - Earliest claimed: 2021-08-19 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Steven J. Battle; Brian D. Barrick; Dung Q. Nguyen; Richard J. Eickemeyer; John B. Griswell, JR.; Balaram Sinharoy; Brian W. Thompto; Tu-An T. Nguyen - Web page: https://patentgrep.com/patent/US20230053981A1 ## CPC - G06F 9/30058: {Conditional branch instructions} - G06F 9/30101: {Special purpose registers} - G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX} - G06F 9/30116: {Shadow registers, e.g. coupled registers, not forming part of the register space} - G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction. ## Claims ### Claim 1 A computer-implemented method comprising: determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction; determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction; determining a predicted result of the compare instruction; completing the conditional branch instruction using the predicted result prior to executing the compare instruction writing a first instruction tag into a conditional register mapper; setting a first bit to one in the conditional register mapper based on the first instruction comprising a compare instruction; and setting a second bit to zero in the conditional register mapper based on the first instruction not being executed and written back. ### Claim 2 (depends on 1) The computer-implement method of claim 1, further comprising executing the compare instruction to determine a calculated result. ### Claim 3 (depends on 2) The computer-implemented method of claim 2, further comprising: determining a branch miss based on the calculated result not matching the predicted result; and performing a pipeline flush responsive to the branch miss. ### Claim 4 (depends on 1) The computer-implemented method of claim 1, wherein the predicted result of the compare instruction is determined based on a branch prediction algorithm. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, further comprising: writing the predicted result of the compare instruction to a first field of a compare info queue, wherein the compare info queue comprises a register. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, wherein the first instruction is written into an issue queue. ### Claim 7 (canceled) ### Claim 8 A system comprising: a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising: determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction; determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction; determining a predicted result of the compare instruction; completing the conditional branch instruction using the predicted result prior to executing the compare instruction; and writing a first instruction tag into a conditional register mapper; setting a first bit to one in the conditional register mapper based on the first instruction comprising a compare instruction; setting a second bit to zero in the conditional register matter based on the first instruction not being executed and written back. ### Claim 9 (depends on 8) The system of claim 8, wherein the operations further comprise: executing the compare instruction to determine a calculated result. ### Claim 10 (depends on 9) The system of claim 9, wherein the operations further comprise: determining a branch miss based on the calculated result not matching the predicted result; and performing a pipeline flush responsive to the branch miss. ### Claim 11 (depends on 8) The system of claim 8, wherein the predicted result of the compare instruction is determined based on a branch prediction algorithm. ### Claim 12 (depends on 8) The system of claim 8, wherein the operations further comprise: writing the predicted result of the compare instruction to a first field of a compare info queue, wherein the compare info queue comprises a register. ### Claim 13 (depends on 8) The system of claim 8, wherein the first instruction is written into an issue queue. ### Claim 14 (canceled) ### Claim 15 A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising: determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction; determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction; determining a predicted result of the compare instruction; completing the conditional branch instruction using the predicted result and writing a first instruction tag into a conditional register mapper; setting a first bit to one in the conditional register mapper based on the first instruction comprising a compare instruction; setting a second bit to zero in the conditional register matter based on the first instruction not being executed and written back. ### Claim 16 (depends on 15) The computer program product of claim 15, wherein the operations further comprise: executing the compare instruction to determine a calculated result. ### Claim 17 (depends on 16) The computer program product of claim 16, wherein the operations further comprise: determining a branch miss based on the calculated result not matching the predicted result; and performing a pipeline flush responsive to the branch miss. ### Claim 18 (depends on 15) The computer program product of claim 15, wherein the predicted result of the compare instruction is determined based on a branch prediction algorithm. ### Claim 19 (depends on 15) The computer program product of claim 15, wherein the operations further comprise: writing the predicted result of the compare instruction to a first field of a compare info queue, wherein the compare info queue comprises a register. ### Claim 20 (depends on 15) The computer program product of claim 15, wherein the first instruction is written into an issue queue.