# US 2023/0053960 A1 · Semiconductor device contact pad and method of contact pad fabrication

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- Number: US 2023/0053960 A1
- Document ID: US20230053960A1
- Status: Published application
- Kind: A1
- Application number: 17/408,257
- Filed: 2021-08-20
- Published: 2023-02-23
- Earliest claimed: 2021-08-20
- Assignees: OmniVision Technologies, Inc.
- Applicants: Omnivision Technologies, Inc.
- Inventors: Hui Zang
- Web page: https://patentgrep.com/patent/US20230053960A1

## CPC

- H10F 39/026: {Wafer-level processing}
- H10F 39/028: {performed after manufacture of the image sensors, e.g. annealing, gettering of impurities, short-circuit elimination or recrystallisation}
- H10F 39/182: {Colour image sensors}
- H10F 39/811: {Interconnections}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A method for forming a contact pad of a semiconductor device is disclosed. The method includes providing a semiconductor substrate including a first side and a second side. The semiconductor device includes a shallow trench isolation structure, disposed between the first side and the second side, and an intermetal dielectric stack coupled to the second side. The intermetal dielectric stack includes a first metal interconnect. The method further includes etching a first trench into the semiconductor substrate, depositing a dielectric material into the first trench to form a dielectric spacer extending along side walls of the first trench, etching a second trench aligned with the first trench, and depositing a metal material into the second trench to form the contact pad that contacts the first metal interconnect.

## Claims

### Claim 1

A method for forming a contact pad of a semiconductor device, the method comprising:
providing a semiconductor substrate including a first side and a second side opposite the first side, wherein the semiconductor device includes a shallow trench isolation (STI) structure disposed between the first side and the second side of the semiconductor substrate, wherein the semiconductor device further includes an intermetal dielectric stack coupled to the second side of the semiconductor substrate, and wherein the intermetal dielectric stack includes a first metal interconnect;
etching a first trench into the semiconductor substrate during a first etching step, wherein the first trench extends from the first side of the semiconductor substrate to the STI structure;
depositing a dielectric material into the first trench during a dielectric deposition step to form a dielectric spacer extending along side walls of the first trench;
etching a second trench aligned with the first trench during a second etching step based, at least in part, on the dielectric spacer, wherein the second trench extends through the STI structure to the first metal interconnect; and
depositing a metal material into the second trench during a metal deposition step to form the contact pad, wherein the contact pad contacts the first metal interconnect.

### Claim 2 (depends on 1)

The method of claim 1, wherein a first width of the first trench is greater than a second width of the second trench, and wherein the second width is defined based on a difference between the first width and a thickness of the dielectric spacer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
depositing an etch stop layer and overlaying the etch stop layer with a pattern using a photomask for at least forming the first trench, and wherein the etch stop layer is deposited before the dielectric material such that the etch stop layer is disposed between the dielectric material and the first side of the semiconductor substrate.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
anisotropically etching the dielectric material during an anisotropic etch step after the dielectric deposition step, wherein during the dielectric deposition step the dielectric material conformally coats the etch stop layer, the side walls of the first trench, and an exposed region of the STI structure, and wherein the anisotropic etch step removes the dielectric material coating the etch stop layer and the exposed region of the STI structure to form the dielectric spacer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the metal material at least partially fills the first trench and the second trench such that the metal material is laterally surrounded by the dielectric spacer, and wherein the metal material further extends over the etch stop layer such that the etch stop layer is disposed between the metal material and the first side of the semiconductor substrate.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
etching the metal material during a metal etch step to remove excess portions of the metal material contacting the etch stop layer and further remove a portion of the metal material laterally surrounded by the dielectric spacer in the first trench to form the contact pad; and
removing the etch stop layer.

### Claim 7 (depends on 3)

The method of claim 3, wherein the second etching step, which forms the second trench with the second width less than the first width of the first trench, is performed using the photomask and without any additional photomasks.

### Claim 8 (depends on 1)

The method of claim 1, wherein the metal material conformally contacts the dielectric spacer to form a third trench disposed between metal side walls of the metal material.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
depositing a second etch stop layer into the third trench such that the second etch stop layer is disposed between the metal side walls of the metal material, wherein the metal material includes a first segment disposed between the second etch stop layer and the first metal interconnect, and wherein other segments of the metal material not disposed between the second etch stop layer and the first metal interconnect form the metal side walls;
etching the other segments of the metal material to remove the metal side walls and form the contact pad, wherein the contact pad is disposed between the second etch stop layer and the first metal interconnect; and
removing the second etch stop layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein a first height of the contact pad is less than a first depth of the second trench, and wherein the first depth of the second trench corresponds to a distance from the first metal interconnect to a first interface where the dielectric spacer contacts the STI structure.

### Claim 11 (depends on 1)

The method of claim 1, wherein the semiconductor substrate corresponds a semiconductor wafer including a plurality of dies, each die included in the plurality of dies corresponding to an instance of the semiconductor device, and wherein each of the plurality of dies are separated from one another by scribe lines indicative of where to dice the semiconductor wafer.

### Claim 12 (depends on 11)

The method of claim 11, wherein at least one die, included in the plurality of dies, includes a second contact pad disposed within a backside scribe line region of the at least one die, wherein the second contact pad is disposed proximate to at least one of the scribe lines, and wherein the second contact pad disposed within the backside scribe line region is formed simultaneously with the contact pad during the first etching step, the dielectric deposition step, the second etching step, and the metal deposition step.

### Claim 13 (depends on 11)

The method of claim 11, wherein the semiconductor device is an image sensor.

### Claim 14

A semiconductor device, comprising:
a semiconductor substrate including a first side and a second side opposite the first side;
a shallow trench isolation (STI) structure disposed within the semiconductor substrate between the first side and the second side;
an intermetal dielectric stack coupled to the second side of the semiconductor substrate, wherein the intermetal dielectric stack includes a first metal interconnect;
a dielectric spacer extending from at least the first side of the semiconductor substrate to the STI structure; and
a contact pad laterally surrounded by the dielectric spacer, and wherein the contact pad contacts the first metal interconnect.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein a portion of the dielectric spacer separates the contact pad from the semiconductor substrate and contacts the STI structure to form a first interface.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the contact pad contacts the STI structure and the first interface where the dielectric spacer contacts the STI structure.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the contact pad includes a metal material that forms metal side walls disposed between the dielectric spacer, and wherein the semiconductor device further includes a secondary metal of the contact pad that is surrounded by the metal material, wherein the metal side walls of the metal material are disposed between the secondary metal and the dielectric spacer.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, further comprising an image pixel and control circuitry for the image pixel, and wherein the contact pad is electrically coupled to at least one of the image pixel or the control circuitry via the first metal interconnect.

### Claim 19

A semiconductor wafer, comprising:
a plurality of dies, each die included in the plurality of dies corresponding to an instance of a semiconductor device, wherein each of the plurality of dies are separated from one another by scribe lines indicative of where to dice the semiconductor wafer, and wherein the semiconductor device includes:
a semiconductor substrate including a first side and a second side opposite the first side, wherein the semiconductor substrate corresponds to a portion of the semiconductor wafer defined by the scribe lines;
a shallow trench isolation (STI) structure disposed within the semiconductor substrate between the first side and the second side;
an intermetal dielectric stack coupled to the second side of the semiconductor substrate, wherein the intermetal dielectric stack includes a first metal interconnect;
a dielectric spacer extending from at least the first side of the semiconductor substrate to the STI structure; and
a contact pad laterally surrounded by the dielectric spacer, and wherein the contact pad contacts the first metal interconnect.

### Claim 20 (depends on 19)

The semiconductor wafer of claim 19, wherein for the semiconductor device of each of the plurality of dies:
the dielectric spacer contacts the STI structure to form a first interface; and
the contact pad contacts the STI structure and the first interface.