# US 2023/0053623 A1 · Semiconductor memory devices and methods of manufacturing thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0053623 A1 - Document ID: US20230053623A1 - Status: Published application - Kind: A1 - Application number: 17/408,098 - Filed: 2021-08-20 - Published: 2023-02-23 - Earliest claimed: 2021-08-20 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Meng-Han Lin; Chia-En Huang - Web page: https://patentgrep.com/patent/US20230053623A1 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/10: characterised by the top-view layout - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 90/00: Package configurations - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device comprising a source, and a drain spaced apart from the source in a first direction. A channel layer is disposed radially outwards of at least one radially outer surface of the source and the drain in a second direction perpendicular to the first direction, the channel layer extending in the first direction. A memory layer is disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction. A contact structure is interposed between the channel layer and at least a portion of the source and/or the drain, the contact structure having a lower resistance than the channel layer. ## Claims ### Claim 1 A semiconductor device, comprising: a source; a drain spaced apart from the source in a first direction; a channel layer disposed radially outwards of at least one radially outer surface of the source and the drain in a second direction perpendicular to the first direction, the channel layer extending in the first direction; a memory layer disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction; and a contact structure interposed between the channel layer and at least a portion of the source and/or the drain, the contact structure having a lower resistance than the channel layer. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the contact structure comprises: a first contact structure wrapped around the drain; and a second contact structure wrapped around the source. ### Claim 3 (depends on 2) The semiconductor device of claim 2, further comprising: a gate extension structure disposed between a portion of the drain and a corresponding portion of the channel layer, the gate extension structure extending in the first direction at least part way towards to the source, wherein a portion the first contact structure is interposed between the gate extension structure and the drain. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the drain has a drain first width in the second direction at locations proximate to the gate extension structure, and a drain second width in the second direction at locations distal from the gate extension structure, the drain second width being larger than the drain first width. ### Claim 5 (depends on 3) The semiconductor device of claim 3, wherein a first axial end of the gate extension structure is disposed axially outwards of an axially inward edge of the first contact structure that is proximate to the source in the first direction, and a second axial end of the gate extension structure opposite the first axial end is axially aligned with the axially inward edge of the first contact structure. ### Claim 6 (depends on 2) The semiconductor device of claim 2, wherein the first contact structure has a first contact structure width which is about equal to a second contact structure width of the second contact structure. ### Claim 7 (depends on 2) The semiconductor device of claim 2, wherein the first contact structure has a first contact structure width which is different from a second contact structure width of the second contact structure. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor device comprises: a plurality of gate layers; and a stack disposed on a radially outer surface of the memory layer in the second direction, the stack comprising a plurality of insulating layers and the plurality of gate layers alternatively stacked on top each other. ### Claim 9 A semiconductor die, comprising: an array of semiconductor devices, each row of the array of semiconductor devices extending in a first direction, each semiconductor device comprising: a source, a drain spaced apart from the source in the first direction, a channel layer disposed radially outwards of at least one radially outer surface of the source and the drain in a second direction perpendicular to the first direction, the channel layer extending in the first direction, a memory layer disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction, at least one gate layer disposed on a radially outer surface of the memory layer in the second direction and extending in the first direction, a gate extension structure disposed between the drain and the channel layer such that at least a portion of a gate length of each semiconductor device is defined by each of the gate extension structures, and a contact structure wrapped around the drain such that a first portion of the contact structure is interposed between the channel layer and the drain, and a second portion of the contact structure is interposed between the gate extension structure and the drain, the contact structure having a lower resistance than the channel layer. ### Claim 10 (depends on 9) The semiconductor die of claim 9, wherein a first axial end of the gate extension structure is disposed axially outwards of an axially inward edge of the first contact structure that is proximate to the source in the first direction, and a second axial end of the gate extension structure opposite the first axial end is axially aligned with the axially inward edge of the first contact structure. ### Claim 11 (depends on 10) The semiconductor die of claim 10, wherein the drain has a drain first width in the second direction at locations proximate to the gate extension structure, and a drain second width in the second direction at locations distal from the gate extension structure, the drain second width being larger than the drain first width. ### Claim 12 (depends on 9) The semiconductor die of claim 9, wherein the contact structure is a first contact structure, the contact structure further comprising: a second contact structure wrapped around the source such that a portion of the second contact structure is interposed between the source and the channel layer. ### Claim 13 (depends on 12) The semiconductor die of claim 12, wherein the first contact structure has a first contact structure width which is about equal to a second contact structure width of the second contact structure. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein the first contact structure has a first contact structure width which is different from a second contact structure width of the second contact structure. ### Claim 15 (depends on 9) The semiconductor die of claim 9, wherein each semiconductor device disposed in a first row of the semiconductor die is parallel to and axially aligned in the first direction with another semiconductor device disposed in a second row that is parallel to the first row in the second direction. ### Claim 16 (depends on 9) The semiconductor die of claim 9, wherein each semiconductor device disposed in a first row of the semiconductor die is parallel to and axially offset in the first direction with another semiconductor device disposed in a second row that is parallel to the first row in the second direction. ### Claim 17 (depends on 9) The semiconductor die of claim 9, wherein each semiconductor device disposed in a first row of the semiconductor die is oriented in a first orientation, and each semiconductor device disposed in a second row that is parallel to the first row is oriented in a second orientation that is opposite of the first orientation. ### Claim 18 A method of making a semiconductor device, comprising: providing a stack comprising a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on top of each other, the stack extending in a first direction; forming a plurality of gate layers by replacing the plurality of sacrificial layers; forming a memory layer extending along the first direction radially inwards of and coupled to the plurality of gate layers in a second direction perpendicular to the first direction; forming a channel layer extending along the first direction and coupled to a radially inner surface of the memory layer in the second direction; forming a contact structure having a lower resistance than the channel layer; and forming a source and a drain spaced apart from the source in the first direction, such that the contact structure is interposed between the channel layer and at least a portion of the source and/or the drain. ### Claim 19 (depends on 18) The method of claim 18, wherein the contact structure comprises: a first contact structure wrapped around the drain; and a second contact structure wrapped around the source. ### Claim 20 (depends on 19) The method of claim 19, further comprising: forming gate extension structures extending along portions of the channel layer in the first direction, and coupled to a radially inner surface of the channel layer, wherein a portion the first contact structure is interposed between the gate extension structure and the drain.