# US 2023/0053595 A1 · Field effect transistor with multi-metal gate via and method

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- Number: US 2023/0053595 A1
- Document ID: US20230053595A1
- Status: Published application
- Kind: A1
- Application number: 17/407,083
- Filed: 2021-08-19
- Published: 2023-02-23
- Earliest claimed: 2021-08-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Sheng-Tsung WANG; Lin-Yu HUANG; Cheng-Chi CHUANG; Sung-Li WANG; Chih-Hao WANG
- Web page: https://patentgrep.com/patent/US20230053595A1

## CPC

- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6729: {characterised by the electrodes}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/42: Vias, e.g. via plugs
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.

## Claims

### Claim 1

A device, comprising:
a substrate;
a gate structure wrapping around a vertical stack of nanostructure semiconductor channels;
a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels; and
a gate via in contact with the first gate structure, including:
a metal liner layer having a first flowability; and
a metal fill layer having a second flowability higher than the first flowability.

### Claim 2 (depends on 1)

The device of claim 1, wherein the gate via further includes a glue layer, and the metal liner layer is between the glue layer and the metal fill layer.

### Claim 3 (depends on 2)

The device of claim 2, wherein the glue layer is in contact with an interlayer dielectric layer, an etch stop layer, a capping layer and a conductive layer of the gate structure.

### Claim 4 (depends on 3)

The device of claim 3, wherein the conductive layer overlies and is in contact with a dielectric layer of the gate structure and a conductive fill layer of the gate structure.

### Claim 5 (depends on 1)

The device of claim 1, wherein the metal liner layer is in contact with an interlayer dielectric layer, an etch stop layer, a capping layer and a conductive layer of the gate structure.

### Claim 6 (depends on 5)

The device of claim 5, wherein a lower surface of the metal fill layer is at a level between upper and lower surfaces of the interlayer dielectric layer.

### Claim 7

A device comprising:
a substrate;
a first semiconductor channel over the substrate;
a gate structure over and surrounding the semiconductor channel;
a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel;
a source/drain region abutting the second semiconductor channel;
a source/drain contact over the source/drain region, formed of a first conductive material having first conductivity;
a source/drain via in contact with the source/drain contact, formed of the first conductive material; and
a gate via in contact with the gate structure, formed of at least one second conductive material having lower conductivity than the first conductive material.

### Claim 8 (depends on 7)

The device of claim 7, wherein the gate via includes a metal fill layer formed of the second conductive material.

### Claim 9 (depends on 8)

The device of claim 8, wherein the gate via further includes a metal liner layer having higher conductivity and lower flowability than the metal fill layer.

### Claim 10 (depends on 7)

The device of claim 7, further comprising:
a second source/drain via in contact with the source/drain via, formed of a third conductive material; and
a second gate via in contact with the gate via, formed of the third conductive material and having substantially the same height as the second source/drain via.

### Claim 11 (depends on 10)

The device of claim 10, wherein a metal fill layer of the gate via is in contact with the second gate via.

### Claim 12 (depends on 11)

The device of claim 11, wherein a metal liner layer laterally surrounding the metal fill layer is in contact with the second gate via.

### Claim 13 (depends on 10)

The device of claim 10, wherein the third conductive material is substantially the same as the first conductive material.

### Claim 14

A method, comprising:
forming a gate structure over and surrounding nanostructure semiconductor channels over a substrate;
forming a source/drain region over and in the substrate;
forming a source/drain contact in contact with the source/drain region;
forming a gate via by:
forming a first opening exposing the gate structure;
forming a metal liner layer in the first opening; and
forming a first metal fill layer over the metal liner layer of a different material than the metal liner layer; and
forming a source/drain via by:
forming a second opening exposing the source/drain contact; and
forming a second metal fill layer in the second opening of a different material than the first metal fill layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising forming a glue layer in the first opening prior to forming the metal liner layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the metal liner layer includes forming a conformal layer of a material having higher conductivity than the glue layer and the metal fill layer.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the second metal fill layer includes filling a first material having higher conductivity and lower flowability than a second material of the first metal fill layer.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the second metal fill layer includes filling substantially the same material as the source/drain contact.

### Claim 19 (depends on 14)

The method of claim 14, further comprising:
forming an etch stop layer over the gate via and the source/drain via;
forming an interlayer dielectric over the etch stop layer;
forming third openings exposing the gate via and the source/drain via; and
forming a second gate via and a second source/drain via by filling the third openings.

### Claim 20 (depends on 19)

The method of claim 19, wherein filling the third openings includes filling the third openings with substantially the same material as the source/drain contact.