# US 2023/0053582 A1 · System and method for error reporting and handling

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- Number: US 2023/0053582 A1
- Document ID: US20230053582A1
- Status: Published application
- Kind: A1
- Application number: 17/817,476
- Filed: 2022-08-04
- Published: 2023-02-23
- Earliest claimed: 2021-08-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kiran Kumar MURALIDHARAN; Srinivasa Raju Nadakuditi; Vulligadla Amaresh
- Web page: https://patentgrep.com/patent/US20230053582A1

## CPC

- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0706: {the processing taking place on a specific hardware platform or in a specific software environment}
- G06F 11/0781: {Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system for error reporting and handling includes a memory storing an error handler, a processor configured to execute the error handler, and a buffer. The error handler is configured to receive an error message from a system on chip (SOC) platform. The error message indicates a plurality of errors have occurred in the SOC platform, and the buffer stores the error message. Further, the error handler is configured to report the error message using a single interrupt. Further, the error handler is configured to handle the errors in the error message using the single interrupt.

## Claims

### Claim 1

A system for error reporting and handling, comprising:
a memory storing an error handler;
a processor configured to execute the error handler; and
a buffer,
wherein the error handler is configured to:
receive an error message from a system on chip (SOC) platform, wherein the error message indicates a plurality of errors have occurred in the SOC platform, and the buffer stores the error message;
report the error message using a single interrupt; and
handle the plurality of errors in the error message using the single interrupt.

### Claim 2 (depends on 1)

The system of claim 1, wherein the handle of the plurality of errors comprises:
detecting that the plurality of errors have occurred in the SoC platform;
raising an interrupt corresponding to the plurality of errors;
processing the error message based on the interrupt using a firmware unit;
performing at least one action based on the processed error message;
clearing the interrupt; and
performing at least one of i) sending an acknowledgment message for the processed error message and ii) waiting for another interrupt to process.

### Claim 3 (depends on 2)

The system of claim 2, wherein processing the error message using the firmware unit comprises:
determining the error message comprises two errors;
determining a priority among the two errors; and
processing the error message based on the priority.

### Claim 4 (depends on 2)

The system of claim 2, wherein the error handler processes each of the two errors one at a time sequentially.

### Claim 5 (depends on 2)

The system of claim 2, wherein the system comprises at least one design block to hold a design state of the error handler until all the errors are processed by the firmware unit.

### Claim 6 (depends on 1)

The system of claim 1, wherein the error message comprises at least one of a design block identifier (ID), an opcode for each of the errors, and context information for each of the errors.

### Claim 7 (depends on 1)

The system of claim 1, wherein one of the errors is a fatal error, wherein the fatal error comprises at least one of a static random-access memory (SRAM) read error, a SRAM write error, an Advanced eXtensible Interface (AXI) Bus access error, an AXI Bus Parity Error, a counter underflow error, a counter overflow error, a First-in, first-out (FIFO) overflow, a FIFO underflow, a packet field corruption error, accessing un-initialized location, and an unsupported configuration.

### Claim 8

A method for error reporting and handling, comprises:
receiving, by a system, an error message from a system on chip (SOC) platform, wherein the error message indicates that a plurality of errors have occurred in the SOC platform, and the system includes a buffer for storing the error message;
reporting, by the system, the error message using a single interrupt; and
handling, by the system, the plurality of errors in the error message using the single interrupt.

### Claim 9 (depends on 8)

The method of claim 8, wherein the handling comprises:
detecting that the plurality of errors have occurred in the SoC platform;
raising an interrupt corresponding to the plurality of errors;
processing the error message based on the interrupt using a firmware unit;
performing at least one action based on the processed error message;
clearing the interrupt; and
performing at least one of i) sending an acknowledgment message for the processed error message and ii) waiting for another interrupt to process.

### Claim 10 (depends on 9)

The method of claim 9, wherein processing the error message using the firmware unit comprises:
determining the error message comprises two errors;
determining a priority among the two errors; and
processing one of the two error errors based on the priority.

### Claim 11 (depends on 9)

The method of claim 9, wherein the error handler processes each of the two errors one at a time sequentially.

### Claim 12 (depends on 9)

The method of claim 9, wherein the system comprises at least one design block to hold a design state of the error handler until all the errors are processed by the firmware unit.

### Claim 13 (depends on 8)

The method of claim 8, wherein the error message comprises at least one of a design block identifier (ID), an opcode for each of the errors, and context information for each of the errors.

### Claim 14 (depends on 8)

The method of claim 8, wherein one of the errors is a fatal error, wherein the fatal error comprises at least one of a static random-access memory (SRAM) read error, a SRAM write error, an Advanced eXtensible Interface (AXI) Bus access error, an AXI Bus Parity Error, a counter underflow error, a counter overflow error, a First-in, first-out (FIFO) overflow, a FIFO underflow, a packet field corruption error, accessing un-initialized location, and an unsupported configuration.

### Claim 15

A system for error handling, comprising:
a memory storing an error handler;
a processor configured to execute the error handler; and
a buffer,
wherein the error handler is configured to:
receive a plurality of error requests from each of a plurality of hardware blocks of a system on chip, wherein each error request indicates an error has occurred in SoC due to the corresponding hardware block, and the buffer stores an error message including information about the errors; and
handle the errors of the error message using a single interrupt.

### Claim 16 (depends on 15)

The system of claim 15, wherein each error request includes an identifier that identifies the corresponding hardware block and an opcode identifying a type of a corresponding error.

### Claim 17 (depends on 15)

The system of claim 15, wherein the error handler sends an acknowledgement message to one of the hardware blocks after processing the error request associated with the one hardware block.

### Claim 18 (depends on 17)

The system of claim 17, wherein the acknowledgement message includes the identifier and the opcode.

### Claim 19 (depends on 17)

The system of claim 17, wherein each error request further includes context information explaining a corresponding error.

### Claim 20 (depends on 15)

The system of claim 15, wherein the error is one of a static random-access memory (SRAM) read error, a SRAM write error, an Advanced eXtensible Interface (AXI) Bus access error, an AXI Bus Parity Error, a counter underflow error, a counter overflow error, a First-in, first-out (FIFO) overflow, a FIFO underflow, a packet field corruption error, accessing un-initialized location, and an unsupported configuration.