# US 2023/0053451 A1 · Semiconductor device structure and method for forming the same

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- Number: US 2023/0053451 A1
- Document ID: US20230053451A1
- Status: Published application
- Kind: A1
- Application number: 17/980,656
- Filed: 2022-11-04
- Published: 2023-02-23
- Earliest claimed: 2019-01-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng CHING; Zhi-Chang LIN; Kuan-Ting PAN; Chih-Hao WANG; Shi-Ning JU
- Web page: https://patentgrep.com/patent/US20230053451A1

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a first stacked nanostructure and a second stacked nanostructure formed over a substrate;
a dummy fin structure between the first stacked nanostructure and the second stacked nano structure;
a gate structure formed over the first stacked nanostructure and the second stacked nano structure;
a conductive layer formed over the gate structure; and
a capping layer formed over the dummy fin structure, wherein each of the gate structure and the conductive layer is divided into two portions by the capping layer.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a sacrificial layer formed over the conductive layer, wherein a bottom surface of the sacrificial layer is lower than a top surface of the capping layer.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the gate structure comprises a gate dielectric layer, and the gate dielectric layer is in direct contact with the capping layer.

### Claim 4 (depends on 3)

The semiconductor device structure as claimed in claim 3, wherein a top surface of the gate dielectric layer is higher than a top surface of the dummy fin structure.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
an isolation structure formed over the substrate, wherein the dummy fin structure is formed over the isolation structure.

### Claim 6 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein an interface between the isolation structure and the dummy fin structure is lower than a bottommost surface of the first stacked nanostructure.

### Claim 7 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the dummy fin structure is made of low-k dielectric material, and the capping layer is made of high-k dielectric material.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a S/D structure formed adjacent to the first stacked nanostructure, wherein a top surface of the S/D structure is higher than a bottom surface of the capping layer.

### Claim 9 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the dummy fin structure has a U-shaped structure with a recessed middle portion.

### Claim 10

A semiconductor device structure, comprising:
an isolation structure formed over a substrate;
a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure;
a dummy fin structure formed over the isolation structure, wherein the dummy fin structure is between the first stacked nanostructure and the second stacked nano structure; and
a capping layer formed over the dummy fin structure; and
a gate structure formed over the first stacked nanostructure and the second stacked nanostructure; and
a gate spacer layer formed adjacent to the gate structure, wherein a sidewall of the capping layer is aligned with a sidewall of the gate spacer layer.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising:
an inner spacer layer adjacent to the first stacked nanostructure, wherein the inner spacer layer is formed on a sidewall of the dummy fin structure and a sidewall of the capping layer.

### Claim 12 (depends on 11)

The semiconductor device structure as claimed in claim 11, wherein a top surface of the capping layer is substantially leveled with the a top surface of the inner spacer layer.

### Claim 13 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein a width of the isolation structure is greater than a width of the dummy fin structure.

### Claim 14 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising:
a conductive layer formed over the gate structure, wherein a top surface of the conductive layer is lower than a top surface of the capping layer.

### Claim 15 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising:
a hard mask layer directly below the gate spacer layer and over the first stacked nano structure.

### Claim 16 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the dummy fin structure has a U-shaped structure with a recessed middle portion.

### Claim 17

A method for forming a semiconductor device structure, comprising:
forming a first stacked nanostructure and a second stacked nanostructure extending above a substrate, wherein each of the first stacked nanostructure and the second stacked nanostructure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers;
forming a plurality of dummy fin structures over the isolation structure, wherein the dummy fin structures are between the first stacked nanostructure and the second stacked nano structure;
forming a plurality of capping layer over the corresponding dummy fin structures;
removing a portion of the capping layers to expose a top surface of the dummy fin structure, such that a number of the capping layers is smaller than a number of the dummy fin structures;
removing the first semiconductor layers to form a gap between two adjacent second semiconductor layers;
forming a gate structure in the gap and over the exposed dummy fin structure; and
removing a portion of the gate structure, wherein a top surface of the gate structure is higher than a top surface of the exposed dummy fin structure and lower than a top surface of the capping layer.

### Claim 18 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
forming a dummy gate structure over the capping layer, the first stacked nanostructure and the second stacked nanostructure; and
forming a gate spacer layer on sidewalls of the dummy gate structure, wherein the gate spacer layer is formed over the capping layer.

### Claim 19 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
removing a portion of the first semiconductor layers to form a cavity; and
forming an inner spacer layer in the cavity, wherein the capping layer is surrounded by the inner spacer layer.

### Claim 20 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
forming a S/D structure adjacent to the first stacked nanostructure, wherein a top surface of the S/D structure is higher than a bottom surface of the capping layer.