# US 2023/0053440 A1 · Apparatus and methods for producing stable clock signals based on a varying frequency source clock > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0053440 A1 - Document ID: US20230053440A1 - Status: Published application - Kind: A1 - Application number: 17/820,007 - Filed: 2022-08-16 - Published: 2023-02-23 - Earliest claimed: 2021-08-19 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Ivo Leonardus COENEN - Web page: https://patentgrep.com/patent/US20230053440A1 ## CPC - H03K 5/00006: {Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68)} - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal. ## Claims ### Claim 1 A system on a chip (SoC) comprising: a first clock divider configured to: produce, based on an oscillator signal at a first frequency: a first clock signal at the first frequency; and a second clock signal at a second frequency being a division of the first frequency by an integer greater than 1; selectively provide the first clock signal as a first output clock signal when a scaling configuration signal has a first value; selectively provide the second clock signal as the first output clock signal when the scaling configuration signal has a second value; and produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal; and a second clock divider configured to: produce a second output clock signal at a third frequency, the second output clock signal being based on the first output clock signal and the frequency indication signal, the third frequency being a division of the second frequency by an integer greater than or equal to 1. ### Claim 2 (depends on 1) The SoC of claim 1, where the frequency indication signal is a captured frequency indication signal, the SoC further comprising a capture circuit configured to: capture the frequency indication signal based on the first output clock signal; and provide the captured frequency indication signal to the second clock divider. ### Claim 3 (depends on 2) The SoC of claim 2, wherein the capture circuit includes a flip-flop that is clocked on rising edges of the first output clock signal. ### Claim 4 (depends on 1) The SoC of claim 1, further comprising a third clock divider configured to: receive the second output clock signal; and produce, based on the second output clock signal, a third output clock signal at a fourth frequency, the fourth frequency being a division of the third frequency by an integer greater than or equal to 1. ### Claim 5 (depends on 4) The SoC of claim 4, further comprising a fourth clock divider configured to: receive the third output clock signal; and produce, based on the third output clock signal, a fourth output clock signal at a fifth frequency, the fifth frequency being a division of the fourth frequency by an integer greater than or equal to 1. ### Claim 6 (depends on 1) The SoC of claim 1, further comprising a third clock divider configured to: receive the first output clock signal; receive the frequency indication signal; and produce a third output clock signal at a fourth frequency, the third output clock signal being based on the first output clock signal and the frequency indication signal, the fourth frequency being a division of the second frequency by an integer greater than or equal to 1. ### Claim 7 (depends on 1) The SoC of claim 1, wherein the scaling configuration signal is captured by the first clock divider on a rising edge of the first clock signal at a start of a new clock period of the second clock signal, the captured scaling configuration signal controlling multiplexing between the first clock signal and the second clock signal for the first output clock signal. ### Claim 8 (depends on 1) The SoC of claim 1, further comprising digital circuitry operating based on a least one of the first output clock signal or the second output clock signal, wherein: the digital circuitry operates at a first voltage when the first clock signal is selected as the first output clock signal; and the digital circuitry operates a second voltage when the second clock signal is selected as the first output clock signal. ### Claim 9 (depends on 8) The SoC of claim 8, wherein the scaling configuration signal is provided by the digital circuitry. ### Claim 10 (depends on 8) The SoC of claim 8, wherein the first clock divider is further configured to: produce, based on the oscillator signal a third output clock signal at a third frequency, the third frequency being a division of the first frequency by an integer greater than or equal to 1. ### Claim 11 (depends on 10) The SoC of claim 10, further comprising: a clock gate configured to: receive the third output clock signal; receive a first clock gate enable signal provided by the digital circuitry; and provide, based on the third output clock signal and the clock gate enable signal, a first gated clock signal. ### Claim 12 (depends on 8) The SoC of claim 8, wherein the first clock divider is further configured to: produce, based on the oscillator signal a third output clock signal at a third frequency, the third frequency being a division of the first frequency by an integer greater than 1. ### Claim 13 (depends on 12) The SoC of claim 12, further comprising: a clock gate configured to: receive the third output clock signal; receive a first clock gate enable signal provided by the digital circuitry; and provide, based on the third output clock signal and the clock gate enable signal, a first gated clock signal. ### Claim 14 A system on a chip (SoC) comprising: an oscillator configured to produce an oscillator signal at a first frequency; a first clock divider configured to: produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency being a division of the first frequency by an integer greater than 1; selectively provide the first clock signal as a first output clock signal when a scaling configuration signal has a first value; selectively provide the second clock signal as the first output clock signal when the scaling configuration signal has a second value; and produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal; a second clock divider configured to: produce a second output clock signal at a third frequency, the second output clock signal being based on the first output clock signal and the frequency indication signal, the third frequency being a division of the second frequency by an integer greater than or equal to 1; and a third clock divider configured to: produce, based on the second output clock signal, a third output clock signal at a fourth frequency being a division of the third frequency by an integer greater than 1. ### Claim 15 (depends on 14) The SoC of claim 14, further comprising a fourth clock divider configured to: receive the first output clock signal; receive the frequency indication signal; and produce a fourth output clock signal at a fifth frequency, the fourth output clock signal being based on the first output clock signal and the frequency indication signal, the fifth frequency being a division of the second frequency by an integer greater than or equal to 1. ### Claim 16 (depends on 15) The SoC of claim 15, where the frequency indication signal is a captured frequency indication signal, the SoC further comprising a capture circuit configured to: capture the frequency indication signal based on the first output clock signal; and provide the captured frequency indication signal to the fourth clock divider. ### Claim 17 (depends on 14) The SoC of claim 14, where the frequency indication signal is a captured frequency indication signal, the SoC further comprising a capture circuit configured to: capture the frequency indication signal based on the first output clock signal; and provide the captured frequency indication signal to the second clock divider. ### Claim 18 A method for operation a system on a chip (SoC), the method comprising: producing, based on an oscillator signal at a first frequency, a first clock signal at the first frequency; producing, based on the oscillator signal, a second clock signal at a second frequency being a division of the first frequency by an integer greater than 1; selectively, based on a scaling configuration signal: providing the first clock signal as a first output clock signal when the scaling configuration signal has a first value; or providing the second clock signal as the first output clock signal when the scaling configuration signal has a second value; producing a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal; and producing, by a second clock divider, a second output clock signal at a third frequency, the second output clock signal being based on the first output clock signal and the frequency indication signal, the third frequency being a division of the second frequency by an integer greater than or equal to 1. ### Claim 19 (depends on 18) The method of claim 18, further comprising: receiving the second output clock signal at a third clock divider; and producing, by the third clock divider based on the second output clock signal, a third output clock signal at a fourth frequency, the fourth frequency being a division of the third frequency by an integer greater than or equal to 1. ### Claim 20 (depends on 18) The method of claim 18, further comprising a third clock divider configured to: receiving the first output clock signal at a third clock divider; receiving the frequency indication signal at the third clock divider; and producing, by the third clock divider based on the first output clock signal and the frequency indication signal, a third output clock signal at a fourth frequency, the fourth frequency being a division of the second frequency by an integer greater than or equal to 1.