# US 2023/0053433 A1 · Semiconductor device and semiconductor device manufacturing method

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- Number: US 2023/0053433 A1
- Document ID: US20230053433A1
- Status: Published application
- Kind: A1
- Application number: 17/982,005
- Filed: 2022-11-07
- Published: 2023-02-23
- Earliest claimed: 2020-05-14
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Haruhiko SERIZAWA; Tatsuo CHIJIMATSU
- Web page: https://patentgrep.com/patent/US20230053433A1

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
a first semiconductor layer disposed above the substrate;
a first semiconductor region and a second semiconductor region that are disposed above the substrate, the first semiconductor layer being disposed between the first semiconductor region and the second semiconductor region with respect to a first direction in plan view;
a second semiconductor layer disposed above the first semiconductor layer;
a third semiconductor region and a fourth semiconductor region that are disposed above the first semiconductor region and the second semiconductor region, respectively, the second semiconductor layer being disposed between the third semiconductor region and the fourth semiconductor region with respect to the first direction;
a third semiconductor layer disposed above the substrate and disposed side by side with respect to the first semiconductor layer with respect to a second direction different from the first direction in plan view;
a fifth semiconductor region and a sixth semiconductor region disposed above the substrate, the third semiconductor layer being disposed between the fifth semiconductor region and the sixth semiconductor region with respect to the first direction in plan view;
a fourth semiconductor layer disposed above the third semiconductor layer and disposed side by side with respect to the second semiconductor layer with respect to the second direction in plan view;
a seventh semiconductor region and an eighth semiconductor region disposed above the fifth semiconductor region and the sixth semiconductor region, respectively, the fourth semiconductor layer being disposed between the seventh semiconductor region and the eighth semiconductor region with respect to the first direction;
an insulating wall having an insulating property, disposed above the substrate, extending in the first direction, and having a first side surface and a second side surface opposite the first side surface;
a first gate electrode disposed above the first semiconductor layer and the second semiconductor layer, first gate insulating films being disposed between the first gate electrode and the first semiconductor layer and between the first gate electrode and the second semiconductor layer; and
a second gate electrode disposed above the third semiconductor layer and the fourth semiconductor layer, second gate insulating films being disposed between the second gate electrode and the third semiconductor layer and between the second gate electrode and the fourth semiconductor layer,
wherein
the first side surface is in contact with the first semiconductor layer and the second semiconductor layer, and
the second side surface is in contact with the third semiconductor layer and the fourth semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1,
wherein
each of conductivity types of the first semiconductor region and the second semiconductor region is a first conductivity type, and
each of conductivity types of the third semiconductor region and the fourth semiconductor region is a second conductivity type different from the first conductivity type.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2,
wherein
the second semiconductor region and the fourth semiconductor region are electrically connected to each other.

### Claim 4 (depends on 3)

The semiconductor device as claimed in claim 3,
wherein
the second semiconductor region and the fourth semiconductor region are electrically connected to the second gate electrode.

### Claim 5 (depends on 2)

The semiconductor device as claimed in claim 2,
wherein
each of conductivity types of the fifth semiconductor region and the sixth semiconductor region is the second conductivity type, and
each of conductivity types of the seventh semiconductor region and the eighth semiconductor region is the first conductivity type.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5,
wherein
the sixth semiconductor region and the eighth semiconductor region are electrically connected to each other.

### Claim 7

The semiconductor device as claimed in claim, 1, further comprising:
a first power supply line electrically connected to the first semiconductor region; and
a second power supply line electrically connected to the fifth semiconductor region.

### Claim 8 (depends on 7)

The semiconductor device as claimed in claim 7,
wherein
the first power supply line and the second power supply line are embedded in the substrate.

### Claim 9

A semiconductor device manufacturing method comprising:
forming a first-semiconductor-material layer above a substrate;
forming a second-semiconductor-material layer above the first-semiconductor-material layer;
forming a first fin and a second fin extending in a first direction in plan view and arranged in a second direction different from the first direction by etching stacked layers including the first-semiconductor-material layer and the second-semiconductor-material layer, the first fin including a first semiconductor layer obtained from the first-semiconductor-material layer and a second semiconductor layer obtained from the second-semiconductor-material layer, the second fin including a third semiconductor layer obtained from the first-semiconductor-material layer and a fourth semiconductor layer obtained from the second-semiconductor-material layer;
forming an insulating wall having an insulating property between the first fin and the second fin, the insulating wall having a first side surface in contact with the first semiconductor layer and the second semiconductor layer and a second side surface in contact with the third semiconductor layer and the fourth semiconductor layer;
forming a first semiconductor region and a second semiconductor region, the first semiconductor layer being disposed between the first semiconductor region and the second semiconductor region with respect to the first direction;
forming a third semiconductor region and a fourth semiconductor region, the second semiconductor layer being disposed between the third semiconductor region and the fourth semiconductor region with respect to the first direction;
forming a fifth semiconductor region and a sixth semiconductor region, the third semiconductor layer being disposed between the fifth semiconductor region and the sixth semiconductor region with respect to the first direction;
forming a seventh semiconductor region and an eighth semiconductor region, the fourth semiconductor layer being disposed between the seventh semiconductor region and the eighth semiconductor region with respect to the first direction;
forming a first gate electrode above the first semiconductor layer and the second semiconductor layer, first gate insulating films being disposed between the first gate electrode and the first semiconductor layer and between the first gate electrode and the second semiconductor layer; and
forming a second gate electrode above the third semiconductor layer and the fourth semiconductor layer, second gate insulating films being disposed between the second gate electrode and the third semiconductor layer and between the second gate electrode and the fourth semiconductor layer.