# US 2023/0053384 A1 · Detecting data bus drive faults > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0053384 A1 - Document ID: US20230053384A1 - Status: Published application - Kind: A1 - Application number: 17/880,220 - Filed: 2022-08-03 - Published: 2023-02-23 - Earliest claimed: 2021-08-18 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Melissa I. Uribe - Web page: https://patentgrep.com/patent/US20230053384A1 ## CPC - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid. ## Claims ### Claim 1 An apparatus, comprising: a set of data pins; a pin associated with communicating error correction information; a first circuit coupled with the set of data pins and configured to bias the set of data pins to a first voltage level in response to the set of data pins being in an idle state; and a second circuit coupled with the pin and configured to bias the pin to a second voltage level in response to the pin being in the idle state, the second voltage level being different than the first voltage level. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising: a ground reference configured to supply the first voltage level; and a voltage source configured to supply the second voltage level. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein: the first circuit comprises a first impedance positioned between the set of data pins and the ground reference, and the second circuit comprises a second impedance positioned between the pin and the voltage source. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising: a driver coupled with the pin and configured to apply a sequence of voltages to the pin, wherein the sequence of voltages applied by the driver are configured to override the second voltage level applied by the second circuit. ### Claim 5 (depends on 1) The apparatus of claim 1, further comprising: a first set of data lines coupled with the set of data pins, wherein the first circuit is coupled with the first set of data lines; and a line associated with communicating the error correction information and coupled with the pin, wherein the second circuit is coupled with the line. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising: a bus configured to receive commands from a host device. ### Claim 7 A method, comprising: applying, in response to a set of data pins being in an idle state, a first voltage to the set of data pins; outputting, by the set of data pins, a first signal based at least in part on applying the first voltage to the set of data pins; applying, in response to a pin associated with communicating error correction information being in the idle state, a second voltage to the pin, the second voltage being different than the first voltage; and outputting, by the pin, a second signal based at least in part on applying the second voltage to the pin, a validity of the first signal being indicated by the second signal. ### Claim 8 (depends on 7) The method of claim 7, further comprising: receiving a command associated with reading data stored at a memory device; retrieving a set of data in response to the command; and applying, based at least in part on the set of data, a set of voltages to the set of data pins during a first duration of a read operation triggered by the command. ### Claim 9 (depends on 8) The method of claim 8, further comprising: generating an error correction code for the set of data based at least in part on retrieving the set of data; and applying, based at least in part on the error correction code, a second set of voltages to the pin during a second duration of the read operation. ### Claim 10 (depends on 9) The method of claim 9, wherein the second set of voltages applied to the pin overrides the second voltage applied to the pin. ### Claim 11 (depends on 9) The method of claim 9, wherein the error correction code indicates a validity of the set of data. ### Claim 12 (depends on 7) The method of claim 7, wherein the second signal output by the pin represents an error correction code that indicates a validity of a set of data represented by the first voltage during a first duration of a read operation. ### Claim 13 (depends on 7) The method of claim 7, wherein the first signal and the second signal are configured to indicate an absence of a valid read operation executed by a memory device based at least in part on the first signal having the first voltage during a first duration of a read operation and the second signal having the second voltage during a second duration of the read operation. ### Claim 14 (depends on 7) The method of claim 7, wherein the second voltage is applied to the pin based at least in part on a circuit that couples the pin with a voltage source. ### Claim 15 A method, comprising: transmitting, to a memory device, a command associated with reading data stored at the memory device; detecting, based at least in part on transmitting the command and during a first time period associated with communicating data requested by the command, a set of signals at a set of data pins, wherein each signal of the set of signals comprises a first voltage level; detecting, based at least in part on transmitting the command and during a second time period associated with communicating error correction information for the data requested by the command, a signal at a pin associated with communicating the error correction information, wherein the signal comprises a second voltage level; determining the data associated with the set of signals is invalid based at least in part on a voltage of each signal of the set of signals being equivalent to the first voltage level for the first time period and a voltage of the signal being equivalent to the second voltage level for the second time period; and discarding the data based at least in part on determining the data is invalid. ### Claim 16 (depends on 15) The method of claim 15, further comprising: generating, based at least in part on the set of signals detected at the set of data pins, a first error correction code based at least in part on a set of data represented by the set of signals; determining, based at least in part on the signal detected at the pin, a second error correction code; and comparing the first error correction code with the second error correction code. ### Claim 17 (depends on 16) The method of claim 16, wherein determining that the data associated with the set of signals is invalid comprises: determining that the data associated with the set of signals is invalid based at least in part on the first error correction code being different than the second error correction code. ### Claim 18 (depends on 16) The method of claim 16, further comprising: determining that a read operation associated with the command is invalid based at least in part on the first error correction code being different than the second error correction code, wherein the data associated with the set of signals is determined as invalid based on determining that the read operation is invalid. ### Claim 19 (depends on 15) The method of claim 15, further comprising: entering a mode of operation associated with ignoring data received from the memory device based at least in part on determining that the data is invalid. ### Claim 20 (depends on 15) The method of claim 15, wherein the voltage of the signal is equivalent to the second voltage level for the second time period based at least in part on a circuit that couples the pin with a voltage source. ### Claim 21 (depends on 15) The method of claim 15, wherein the first time period and the second time period overlap. ### Claim 22 An apparatus, comprising: a memory array comprising an array of memory cells that each comprise capacitive storage elements; and a circuit coupled with the memory array and configured to cause the apparatus to: apply, in response to a set of data pins being in an idle state, a first voltage to the set of data pins; output, by the set of data pins, a first signal based at least in part on the first voltage being applied to the set of data pins; apply, in response to a pin associated with communicating error correction information being in the idle state, a second voltage to the pin, the second voltage being different than the first voltage; and output, by the pin, a second signal based at least in part on the second voltage being applied to the pin, a validity of the first signal being indicated by the second signal. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the circuit is further configured to cause the apparatus to: receive a command associated with reading data stored at a memory device; retrieve a set of data in response to the command; and apply, based at least in part on the set of data, a set of voltages to the set of data pins during a first duration of a read operation triggered by the command. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the circuit is further configured to cause the apparatus to: generate an error correction code for the set of data based at least in part on retrieving the set of data; and apply, based at least in part on the error correction code, a second set of voltages to the pin during a second duration of the read operation. ### Claim 25 (depends on 22) The apparatus of claim 22, wherein the second signal output by the pin represents an error correction code that indicates a validity of a set of data represented by the first voltage during a first duration of a read operation. ### Claim 26 An apparatus, comprising: a memory array comprising an array of memory cells that each comprise capacitive storage elements; and a circuit coupled with the memory array and configured to cause the apparatus to: transmit, to a memory device, a command associated with reading data stored at the memory device; detect, based at least in part on transmitting the command and during a first time period associated with communicating data requested by the command, a set of signals at a set of data pins, wherein each signal of the set of signals comprises a first voltage level; detect, based at least in part on transmitting the command and during a second time period associated with communicating error correction information for the data requested by the command, a signal at a pin associated with communicating the error correction information, wherein the signal comprises a second voltage level; determine the data associated with the set of signals is invalid based at least in part on a voltage of each signal of the set of signals being equivalent to the first voltage level for the first time period and a voltage of the signal being equivalent to the second voltage level for the second time period; and discard the data based at least in part on determining the data is invalid. ### Claim 27 (depends on 26) The apparatus of claim 26, wherein the circuit is further configured to cause the apparatus to: generate, based at least in part on the set of signals detected at the set of data pins, a first error correction code based at least in part on a set of data represented by the set of signals; determine, based at least in part on the signal detected at the pin, a second error correction code; and compare the first error correction code with the second error correction code. ### Claim 28 (depends on 27) The apparatus of claim 27, wherein the circuit is further configured to cause the apparatus to: determine that the data associated with the set of signals is invalid based at least in part on the first error correction code being different than the second error correction code. ### Claim 29 (depends on 27) The apparatus of claim 27, wherein the circuit is further configured to cause the apparatus to: determine that the data associated with the set of signals is invalid based at least in part on the first error correction code being different than the second error correction code. ### Claim 30 (depends on 26) The apparatus of claim 26, wherein the circuit is further configured to cause the apparatus to: enter a mode of operation associated with ignoring data received from the memory device based at least in part on determining that the data is invalid.