Low-power flip flop circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chia LAI, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
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Abstract
A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
Claims20
A method to operate a flip-flop circuit, comprising:
- receiving a scan-in signal and a data signal;
- selectively coupling either the scan-in signal or the data signal to coupled master and slave latches;
- and
- based on a clock signal, selectively activating either the master latch or the slave latch so as to latch either the scan-in signal or the data signal as an output signal of the flip-flop circuit.
A method of operating a flip-flop circuit, comprising:
- in response to a clock signal, complementarily activating first and second latch circuits so as to latch a first input signal to an output signal via the first latch circuit, or latch a second input signal to the output signal via the second latch circuit;
- and
- delaying the clock signal to the first latch circuit, but not delaying the clock signal to the second latch circuit.
A method of operating a flip-flop circuit, the method, comprising:
- receiving a clock signal by a first circuit;
- receiving the clock signal by a second circuit coupled to the first circuit;
- activating the first circuit in response to the clock signal to couple a first input signal to an output of the flip-flop circuit;
- subsequently deactivating the first circuit and activating the second circuit in response to the clock signal to couple a second input signal to the output of the flip-flop circuit;
- and
- delaying the clock signal to the first circuit, but not delaying the clock signal to the second circuit.
Dependencies are inferred from the claim text.