Clock enabler circuit
AssigneeSony Semiconductor Solutions Corporation
InventorYOSHINORI TANAKA
Life of this patent
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Abstract
An unnecessary circuit operation in a clock enabler circuit accompanying toggling of a clock signal is suppressed. A state holding unit performs a holding operation of a state as to whether or not to output an output clock signal according to an internal clock signal. A clock signal output unit controls output of the output clock signal according to the state held in the state holding unit. A control unit supplies, to the state holding unit, the internal clock signal and a value of the state that are necessary for the holding operation in the state holding unit on a basis of a clock signal and a clock enable signal from an outside.
Claims11
A clock enabler circuit comprising:
- a state holding unit that performs a holding operation of a state as to whether or not to output an output clock signal according to an internal clock signal;
- a clock signal output unit that controls output of the output clock signal according to the state held in the state holding unit;
- and
- a control unit that supplies, to the state holding unit, the internal clock signal and a value of the state that are necessary for the holding operation on a basis of a clock signal and a clock enable signal from an outside.
Dependencies are inferred from the claim text.