System, method, and apparatus for sris mode selection for pcie
AssigneeIntel Corporation
InventorsDavid J. Harriman, Debendra Das Sharma, Daniel S. Froelich, Sean O. Stalley
Life of this patent
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Abstract
Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.
Claims23
A device comprising:
- a port to couple the device to another device via a link;
- and
- control logic to:
- determine a clocking architecture supported by the another device;
- and
- set a clocking architecture to be used on the link in a Peripheral Component Interconnect Express (PCIe) link control register, wherein the device is to send information to the another device via the link using the set clocking architecture.
A method comprising:
- determining, by a first device, a clocking architecture supported by a second device;
- setting a clocking architecture to be used on a link between the first device and the second device in a Peripheral Component Interconnect Express (PCIe) link control register;
- and
- sending information from the first device to the second device via the link using the set clocking architecture.
A system comprising:
- a host device comprising a first port to support a link;
- and
- an endpoint device comprising a second port to support the link, wherein the host device couples to the endpoint device via the link;
- wherein the host device comprises protocol circuitry to:
- determine a clocking architecture supported by the endpoint device;
- and
- set a clocking architecture to be used on the link in a Peripheral Component Interconnect Express (PCIe) link control register, wherein the host device is to send information to the endpoint device via the link using the set clocking architecture.
Dependencies are inferred from the claim text.