Operating method of floating point operation circuit and integrated circuit including floating point operation circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsJoong Baik Kim, Yongmin Jung
Life of this patent
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Abstract
An operating method of a floating point operation circuit includes, in response to receiving a first instruction, generating a first output by performing a fused multiplication and addition operation on a first input, a second input, and a third input. The method further includes, in response to receiving a second instruction, generating a second output by inverting one input of a fourth input, a fifth input, and a sixth input. Generating the second output includes generating a transform factor and a simplified value from the one input.
Claims20
An operating method of a floating point operation circuit, comprising:
- in response to receiving a first instruction, generating a first output by performing a fused multiplication and addition operation on a first input, a second input, and a third input;
- and
- in response to receiving a second instruction, generating a second output by inverting one input of a fourth input, a fifth input, and a sixth input,
- wherein generating the second output comprises:
- generating a transform factor and a simplified value from the one input.
An operating method of a floating point operation circuit, comprising:
- calculating an inverse value of a divisor of a division operation, based on a second operation mode;
- and
- performing a multiplication operation of a dividend and an inverse value of the divisor, based on a first operation mode,
- wherein calculating the inverse value of the divisor of the division operation, based on the second operation mode comprises:
- generating a transform factor and a simplified value from the divisor, in the second operation mode.
An integrated circuit, comprising:
- a first register;
- a second register;
- a third register;
- a fourth register;
- a fifth register;
- and
- a floating point operation circuit,
- wherein, in a first operation mode, the floating point operation circuit generates a first intermediate value by multiplying a value of the first register and a value of the second register together, generates an output value by adding a value of the third register and the first intermediate value, and stores the output value in the fourth register,
- wherein, in a first phase of a second operation mode, the floating point operation circuit generates a simplified value and a transform factor from a value of the second register, stores the simplified value in the fourth register, and stores the transform factor in the fifth register, and
- wherein a value having a sign opposite to a sign of a value stored in the fourth register is transferred to the first register.
Dependencies are inferred from the claim text.