Methods and devices for digital clock multiplication of a clock to generate a high frequency output
AssigneeIntel Corporation
InventorsAli AZAM, Ashoke RAVI, Benjamin JANN
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Abstract
A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.
Claims20
A digital clock multiplier (DCM) circuit comprising:
- a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifier (SCPA) unit cells configured to:
- receive a phase shift of a driving clock phase;
- and
- one or more processors configured to:
- disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift;
- generate an output signal for each of the plurality of cascade SCPA unit cells;
- and
- combine the output signal for each of the plurality of cascade SCPA unit cells to generate a PA row output signal.
A method comprising:
- receiving a phase shift of a driving clock phase;
- disabling one or more of a plurality of cascade SCPA unit cells of a row of PAs based on a frequency of the phase shift;
- generating an output signal for each of the cascade SCPA unit cells;
- and
- combining the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.
Dependencies are inferred from the claim text.