# US 2022/0406618 A1 · Technologies for aligned vias over multiple layers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0406618 A1 - Document ID: US20220406618A1 - Status: Published application - Kind: A1 - Application number: 17/351,537 - Filed: 2021-06-18 - Published: 2022-12-22 - Earliest claimed: 2021-06-18 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Changhua Liu; Leonel R. Arana; Jeremy D. Ecton; Suddhasattwa Nad; Brandon Christian Marin - Web page: https://patentgrep.com/patent/US20220406618A1 ## CPC - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 70/095: {of vias therein} - H05K 1/181: associated with surface mounted components - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/20: Inductors - H10D 1/716: {having vertical extensions} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 20/084: {for dual-damascene structures} - H10W 20/43: Layouts of interconnections - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/496: {Capacitor integral with wiring layers} - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H05K 1/141: {One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence)} - H05K 3/0082: {characterised by the exposure method of radiation-sensitive masks} - H05K 3/184: {using masks} - H05K 2201/10378: Interposers - H05K 2201/10704: Pin grid array [PGA] - H05K 2201/10719: Land grid array [LGA] - H05K 2203/0369: Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist - H05K 2203/056: Using an artwork, i.e. a photomask for exposing photosensitive layers - H05K 2203/0574: Stacked resist layers used for different processes - H10W 20/0882: {wherein the dual damascene structure is in a photoresist layer} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity, medium-photosensitivity, and low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed. ## Claims ### Claim 1 A method comprising: applying a first layer to a substrate, wherein the first layer comprises a photoimageable dielectric (PID) material; applying a second layer to the first layer, wherein the second layer comprises a PID material or a photoresist material; applying a third layer to the second layer, wherein the third layer comprises a photoresist material; exposing the first layer, the second layer, and the third layer with electromagnetic radiation with use of a multi-tone photomask, wherein the electromagnetic radiation through one or more light gray regions of the multi-tone photomask exposes two but not three of the first layer, second layer, and third layer, and wherein the electromagnetic radiation through one or more dark gray regions of the multi-tone photomask exposes only one of the first layer, second layer, and third layer; developing the first layer, the second layer, and the third layer, wherein the developed first layer defines a first mold with a first via region, wherein the developed second layer defines a second mold with a conductive trace region and a second via region, wherein the developed third layer comprises an overhang region that extends over the second via region; filling the mold defined by the first layer and the mold defined by the second layer with a conductive infill; and applying an etchant to the conductive infill, wherein the etchant etches the conductive infill from a top surface of the conductive infill to create a conductive trace in the conductive trace region, wherein the etchant laterally etches the conductive infill under the overhang region to create a via in the second via region, wherein the etched conductive infill comprises a first via in the first via region, a conductive trace in the conductive trace region, and a second via in the second via region. ### Claim 2 (depends on 1) The method of claim 1, wherein the electromagnetic radiation (i) exposes the first layer, the second layer, and the third layer through the one or more light regions, (ii) exposes the first layer and the third layer through the one or more light gray regions and does not expose the second layer through the one or more light gray regions, (iii) exposes the first layer through the one or more dark gray regions and does not expose the second layer or third layer through the one or more dark gray regions, and (iv) does not expose any of the first layer, the second layer, or the third layer through the one or more dark regions, wherein the one or more dark regions define the first via region, wherein the one or more dark gray regions define the conductive trace region, and wherein the one or more light gray regions define the second via region. ### Claim 3 (depends on 1) The method of claim 1, wherein the first layer comprises a PID material and the second layer comprises a photoresist material, the method further comprising: removing the second layer and the third layer while keeping the first layer in place. ### Claim 4 (depends on 1) The method of claim 1, wherein the first layer comprises a PID material and the second layer comprises a PID material, the method further comprising: removing the third layer while keeping the first layer and the second layer in place. ### Claim 5 (depends on 1) The method of claim 1, wherein a cross-sectional profile of the second via has a concave shape with a narrower region distal from the substrate and a broader region proximal to the substrate. ### Claim 6 (depends on 5) The method of claim 5, wherein the first via has a cross-sectional profile taken parallel to the conductive trace that is linearly tapered. ### Claim 7 (depends on 1) The method of claim 1, wherein the first layer comprises a negative PID material, wherein the second layer comprises a negative photoresist material, and wherein the third layer comprises a negative photoresist material. ### Claim 8 (depends on 1) The method of claim 1, wherein the first layer comprises a negative PID material, wherein the second layer comprises a negative PID material, and wherein the third layer comprises a negative photoresist material. ### Claim 9 (depends on 1) The method of claim 1, wherein the conductive infill comprises copper. ### Claim 10 (depends on 1) The method of claim 1, wherein the substrate comprises silicon. ### Claim 11 (depends on 1) The method of claim 1, wherein the conductive trace has a width between 0.5 and 4 micrometers and a height between 0.5 and 4 micrometers, wherein the first via has a width that is within 0.1 micrometers of the width of the conductive trace, wherein the second via has a width that is within 0.1 micrometers of the width of the conductive trace. ### Claim 12 (depends on 1) The method of claim 1, further comprising: creating a redistribution layer comprising the first via, the second via, and the conductive trace; and packaging the redistribution layer with one or more integrated circuits in a package. ### Claim 13 (depends on 1) The method of claim 1, further comprising creating a capacitor comprising the conductive trace, the first via, and the second via. ### Claim 14 (depends on 1) The method of claim 1, further comprising creating an inductor comprising the conductive trace, the first via, and the second via. ### Claim 15 An apparatus comprising: a plurality of conductive traces on a substrate; a first plurality of vias, wherein individual vias of the first plurality of vias connect individual conductive traces of the plurality of conductive trace to a first layer of the apparatus; and a second plurality of vias, wherein individual vias of the second plurality of vias connect individual conductive traces of the plurality of conductive trace to a second layer of the apparatus different from the first, wherein a pitch of the plurality of conductive traces is less than three times a width of individual conductive traces of the plurality of conductive traces, wherein a pitch of the first plurality of vias is less than three times the width of individual conductive traces of the plurality of conductive traces, wherein a pitch of the second plurality of vias is less than three times the width of individual conductive traces of the plurality of conductive traces. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein individual conductive traces of the plurality of conductive traces have a width between 0.5 and 4 micrometers, wherein individual vias of the first plurality of vias have a width that is within 0.1 micrometers of a width of the connected conductive trace, wherein individual vias of the second plurality of vias have a width that is within 0.1 micrometers of the width of the connected conductive trace. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein a layer surrounding the second plurality of vias comprises a photoimageable dielectric (PID) material. ### Claim 18 (depends on 15) The apparatus of claim 15, wherein a cross-section profile of the second via has a concave shape with a narrower region distal from the substrate and a broader region proximal to the substrate. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the first via has a cross-section taken parallel to the conductive trace that is linearly tapered. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the apparatus is a processor, the processor comprising: one or more processor dies; a redistribution layer connected to the one or more processor dies, the redistribution layer comprising the plurality of conductive traces, the first plurality of vias, and the second plurality of vias.