Hardware accelerator method and device
AssigneeSamsung Electronics Co., Ltd.
InventorsJunki PARK, Joonsang YU, Jun-Woo JANG
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Abstract
A processor-implemented hardware accelerator method includes: receiving input data; loading a lookup table (LUT); determining an address of the LUT by inputting the input data to a comparator; obtaining a value of the LUT corresponding to the input data based on the address; and determining a value of a nonlinear function corresponding to the input data based on the value of the LUT, wherein the LUT is determined based on a weight of a neural network that outputs the value of the nonlinear function.
Claims28
A hardware accelerator, comprising:
- a processor configured to
- receive input data,
- load a lookup table (LUT),
- determine an address of the LUT by inputting the input data to a comparator,
- obtain a value of the LUT corresponding to the input data, and
- determine a value of a nonlinear function corresponding to the input data based on the value of the LUT,
- wherein the LUT is determined based on a weight of a neural network that outputs the value of the nonlinear function.
A processor-implemented hardware accelerator method, the method comprising:
- receiving input data;
- loading a lookup table (LUT);
- determining an address of the LUT by inputting the input data to a comparator;
- obtaining a value of the LUT corresponding to the input data based on the address;
- and
- determining a value of a nonlinear function corresponding to the input data based on the value of the LUT,
- wherein the LUT is determined based on a weight of a neural network that outputs the value of the nonlinear function.
A processor-implemented hardware accelerator method, the method comprising:
- generating a neural network comprising a first layer, an activation function, and a second layer;
- training the neural network to output a value of a nonlinear function;
- transforming the first layer and the second layer of the trained neural network into a single integrated layer;
- and
- generating a LUT for determining the nonlinear function based on the integrated layer.
A processor-implemented hardware accelerator method, the method comprising:
- determining an address of a lookup table (LUT) based on input data of a neural network, wherein the LUT is generated by integrating a first layer and a second layer of the neural network;
- obtaining a value of the LUT corresponding to the input data based on the address;
- and
- determining a value of a nonlinear function corresponding to the input data based on the value of the LUT.
Dependencies are inferred from the claim text.