Back to results
US 2022/0365751 A1Published application
Compressed wallace trees in fma circuits
AssigneeIntel Corporation
InventorsAditya Varma, Mahesh Kumashikar, Michael Espig
Life of this patent
Estimating the term…
Abstract
An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.
Claims21
An apparatus, comprising:
- one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree;
- and
- circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits.
A method, comprising:
- providing one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree;
- and
- providing one or more fractional width FMA operations through the one or more fractional width FMA circuits.
An apparatus, comprising:
- a processor core;
- a memory;
- and
- a fused multiply-accumulate (FMA) unit coupled to the processor core and the memory, wherein the FMA unit comprises one or more fractional width FMA circuits configured as a shared Wallace tree, and wherein the FMA unit is to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits.
1 more element
Dependencies are inferred from the claim text.