Electronic device provided with a stack of two high electron mobility transistors arranged in a bridge half-arm

A structure, comprising:

• an insulating layer;
• a first stack of layers on a first surface of the insulting layer, the first stack of layers including a first group III-V semiconductor layer and a second group III-V semiconductor layer having a different semiconductor material from the first group III-V semiconductor layer, the second group III-V semiconductor layer between the first group III-V semiconductor layer and the first surface of the insulating layer;
• a second stack of layers on a second surface of the insulting layer that is opposite to the first surface, the second stack of layers including a third group III-V semiconductor layer and a fourth group III-V semiconductor layer having a different semiconductor material from the third group III-V semiconductor layer, the fourth group III-V semiconductor layer between the third group III-V semiconductor layer and the second surface of the insulating layer;
• a first electrode in contact with the first group III-V semiconductor layer;
• a second electrode in contact with the first group III-V semiconductor layer, the second electrode separated from the first electrode;
• a third electrode in contact with the third group III-V semiconductor layer and the first electrode, the third electrode separated from the second electrode;
• and
• a fourth electrode in contact with the third group III-V semiconductor layer, the fourth electrode separated from each one of the third electrode, the second electrode or the first electrode.

A method, comprising:

• receiving a first body and a second body,
• wherein the first body includes:
• a first stack of layers on a first surface of a first insulting layer, the first stack of layers including a first group III-V semiconductor layer and a second group III-V semiconductor layer having a different semiconductor material from the first group III-V semiconductor layer, the second group III-V semiconductor layer between the first group III-V semiconductor layer and the first surface of the first insulating layer;
• a first electrode in contact with the first group III-V semiconductor layer and exposed on a second surface of the first insulting layer that is opposite to the first surface;
• a second electrode in contact with the first group III-V semiconductor layer, the second electrode encapsulated by the first insulating layer on the second surface of the first insulating layer;
• wherein the second body includes:
• a second stack of layers on a third surface of a second insulting layer, the second stack of layers including a third group III-V semiconductor layer and a fourth group III-V semiconductor layer having a different semiconductor material from the third group III-V semiconductor layer, the fourth group III-V semiconductor layer between the third group III-V semiconductor layer and the third surface of the second insulating layer;
• a third electrode in contact with the third group III-V semiconductor layer and exposed on a fourth surface of the second insulting layer that is opposite to the third surface;
• a fourth electrode in contact with the third group III-V semiconductor layer, the fourth electrode encapsulated by the second insulating layer on the fourth surface of the second insulating layer;
• and
• bonding the first body and the second body by the second surface of the first body and the fourth surface of the second body, the first electrode aligned with the third electrode.