Semiconductor packages and manufacturing methods for the same
AssigneeSK hynix Inc.
InventorChan Sun LEE
Life of this patent
Estimating the term…
Loading patent…
AssigneeSK hynix Inc.
InventorChan Sun LEE
Estimating the term…
A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.
A semiconductor package comprising:
Dependencies are inferred from the claim text.