Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, comprising:

• forming a plurality of strip patterns and a plurality of island patterns on a substrate, wherein a ratio of a sum area of the plurality of strip patterns and the plurality of island patterns projected onto the substrate and an area of the substrate is in a range from 10% to 90%;
• forming a polysilicon layer to cover the plurality of strip patterns, the plurality of island patterns, and a surface of the substrate uncovered by the plurality of strip patterns and the plurality of island patterns;
• performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of strip patterns and the plurality of island patterns;
• and
• after performing the CMP process, patterning the polysilicon layer to form a logic gate, an erase gate, and a select gate simultaneously.

A method of manufacturing a semiconductor device, comprising:

• providing a substrate having a memory cell region, a logic region, and a dummy region;
• forming a plurality of stack structures on the substrate in the memory cell region and the dummy region;
• forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region;
• and
• performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures, wherein top surfaces of the plurality of stack structures are level with a topmost surface of the polysilicon layer surrounding the plurality of stack structures after performing the CMP process.