Fluid ejection devices including a memory

An integrated circuit comprising:

• a first memory;
• a second memory comprising a plurality of memory elements;
• a control line to access the second memory for read and/or write operations when the second memory is enabled;
• a first switch electrically coupled between the control line and a first side of each memory element of the plurality of memory elements;
• a plurality of second switches, each second switch electrically coupled to a second side of a respective memory element of the plurality of memory elements;
• and
• an ID line electrically coupled to the first memory,
• wherein the second memory is enabled in response to a first logic level on the ID line.

An integrated circuit comprising:

• a control line;
• a first memory;
• a second memory comprising a plurality of memory elements;
• a first transistor having a source-drain path electrically coupled between the control line and a first side of each memory element of the plurality of memory elements;
• a plurality of second transistors, each second transistor having a source-drain path electrically coupled between a respective memory element of the plurality of memory elements and a common node;
• and
• an ID line electrically coupled to the first memory,
• wherein the second memory is enabled in response to a first logic level on the ID line.

An integrated circuit comprising:

• an ID line;
• a control line;
• a first memory to be accessed for read and/or write operations through the ID line;
• a second memory comprising a plurality of memory elements;
• a first switch to electrically connect a first side of each memory element of the plurality of memory elements to the control line in response to a first logic level on the ID line and electrically disconnect the first side of each memory element of the plurality of memory elements from the control line in response to a second logic level on the ID line;
• a plurality of second switches;
• and
• a respective second switch of the plurality of second switches to electrically connect a second side of a respective memory element of the plurality of memory elements to a common node in response to an address signal and the first logic level on the ID line.