# US 2022/0286145 A1 · Pipelined forward error correction for vector signaling code channel

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- Number: US 2022/0286145 A1
- Document ID: US20220286145A1
- Status: Published application
- Kind: A1
- Application number: 17/746,778
- Filed: 2022-05-17
- Published: 2022-09-08
- Earliest claimed: 2017-04-14
- Assignees: Kandou Labs, S.A.
- Applicants: Kandou Labs, S.A.
- Inventors: Amin Shokrollahi; Dario Carnelli
- Web page: https://patentgrep.com/patent/US20220286145A1

## CPC

- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/091: {Parallel or block-wise CRC computation}
- H03M 13/134: {Non-binary linear block codes not provided for otherwise}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- H03M 13/3746: {with iterative decoding}
- H03M 13/616: {Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations}
- H03M 13/6561: {Parallelized implementations}
- H04L 1/0045: {Arrangements at the receiver end}
- H04L 1/0061: {Error detection codes}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

## Claims

### Claim 1

A method comprising:
sequentially receiving a plurality of data symbols, and storing each data symbol as a set of bits in a corresponding deserialization buffer location defined by a unique symbol position index;
generating a first syndrome value from a first pair of multi-bit check words generated by performing bitwise XOR operations on the plurality of data symbols, the first syndrome value corresponding to a bit-error mask of a data symbol having an error;
generating a second syndrome value from a second pair multi-bit check words generated by performing bitwise XOR operations on modulo-multiplied data symbols, each data symbol modulo-multiplied by the unique symbol position index, the second syndrome value corresponding to a modulo-multiplication of the bit-error mask with the unique symbol position index of the data symbol having the error;
calculating the symbol position index of the data symbol having the error by dividing the second syndrome value by the bit-error mask; and
generating a corrected set of output bits by applying the bit-error mask to the stored set of bits in the deserialization buffer location identified by the symbol position index of the data symbol having the error.

### Claim 2 (depends on 1)

The method of claim 1, wherein each syndrome value comprises n bits, and wherein the plurality of data symbols comprises 2n−2 data symbols.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plurality of data symbols are orthogonal differential vector signaling (ODVS) codewords of an ODVS code, and wherein generating each set of output bits comprises decoding the ODVS codewords.

### Claim 4 (depends on 1)

The method of claim 1, wherein dividing the second syndrome value by the bit-error mask comprises forming a binary reciprocal of the bit-error mask, and modulo-multiplying the binary reciprocal of the bit-error mask by the second syndrome value.

### Claim 5 (depends on 4)

The method of claim 4, wherein the binary reciprocal of the bit-error mask is obtained from a lookup table.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first and second pairs of multi-bit check words each comprise a local multi-bit check word generated from the received plurality of data symbols.

### Claim 7 (depends on 6)

The method of claim 6, wherein the local multi-bit check words are incrementally updated responsive to each received plurality of data symbols.

### Claim 8 (depends on 6)

The method of claim 6, wherein the first and second pairs of multi-bit check words each comprise a received multi-bit check word generated from a plurality of transmitted data symbols.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first syndrome value is generated by comparing the local and received multi-bit check words of the first pair of multi-bit check words, and wherein the second syndrome value is generated by comparing the local and received multi-bit check words of the second pair of multi-bit check words.

### Claim 10 (depends on 1)

The method of claim 1, wherein applying the bit-error mask to the set of output bits in the deserialization buffer location comprises performing a bit-wise XOR of the set of output bits in the deserialized buffer location with the bit-error mask to generate the corrected set of output bits.

### Claim 11

An apparatus comprising:
a deserialization buffer configured to sequentially receive a plurality of data symbols, and to store each data symbol as a set of bits in a corresponding deserialization buffer location defined by a unique symbol position index;
a forward error correction (FEC) circuit configured to:
generate a first syndrome value from a first pair of multi-bit check words generated by performing bitwise XOR operations on the plurality of data symbols, the first syndrome value corresponding to a bit-error mask of a data symbol having an error;
generate a second syndrome value from a second pair multi-bit check words generated by performing bitwise XOR operations on modulo-multiplied data symbols, each data symbol modulo-multiplied by the unique symbol position index, the second syndrome value corresponding to a modulo-multiplication of the bit-error mask with the unique symbol position index of the data symbol having the error; and
calculate the symbol position index of the data symbol having the error by dividing the second syndrome value by the bit-error mask; and
the deserialization buffer configured to generate a corrected set of output bits by applying the bit-error mask to the stored set of bits in the deserialization buffer location identified by the symbol position index of the data symbol having the error.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein each syndrome value comprises n bits, and wherein the plurality of data symbols comprises 2n−2 data symbols.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the plurality of data symbols are orthogonal differential vector signaling (ODVS) codewords of an ODVS code, and wherein the apparatus further comprises a plurality of multi-input comparators (MICs) configured to generate each set of output bits by decoding the ODVS codewords.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the FEC circuit is configured to divide the second syndrome value by the bit-error mask by forming a binary reciprocal of the bit-error mask, and modulo-multiplying the binary reciprocal of the bit-error mask by the second syndrome value.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the FEC comprises a lookup table configured to receive the bit-error mask and to output the binary reciprocal of the bit-error mask.

### Claim 16 (depends on 11)

The apparatus of claim 11, wherein the first and second pairs of multi-bit check words each comprise a local multi-bit check word generated from the received plurality of data symbols.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the FEC circuit is configured to incrementally update the local multi-bit check words responsive to each received data symbol of the plurality of data symbols.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein the first and second pairs of multi-bit check words each comprise a received multi-bit check word generated from a plurality of transmitted data symbols.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the FEC circuit is configured to generate the first syndrome value by comparing the local and received multi-bit check words of the first pair of multi-bit check words, and to generate the second syndrome value by comparing the local and received multi-bit check words of the second pair of multi-bit check words.

### Claim 20 (depends on 11)

The apparatus of claim 11, wherein the deserialization buffer is configured to apply the bit-error mask to the set of output bits in the deserialization buffer location by performing a bit-wise XOR of the set of output bits in the deserialized buffer location with the bit-error mask to generate the corrected set of output bits.