# US 2022/0286142 A1 · Guaranteed data compression using intermediate compressed data

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- Number: US 2022/0286142 A1
- Document ID: US20220286142A1
- Status: Published application
- Kind: A1
- Application number: 17/751,583
- Filed: 2022-05-23
- Published: 2022-09-08
- Earliest claimed: 2018-06-29
- Assignees: Imagination Technologies Limited
- Applicants: Imagination Technologies Limited
- Inventors: Simon Fenney
- Web page: https://patentgrep.com/patent/US20220286142A1

## CPC

- H03M 7/30: Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H04N 19/42: characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence)
- G06F 1/035: Reduction of table size {(G06F1/0314 takes precedence)}
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06T 1/60: Memory management
- G06T 9/00: Image coding (bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00)
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H03M 7/3071: {Prediction}
- H03M 7/42: using table look-up for the coding or decoding process, e.g. using read-only memory {(H03M7/4006 takes precedence)}
- H04N 19/186: the unit being a colour or a chrominance component
- H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence)
- H04N 19/426: using memory downsizing methods
- H04N 19/433: characterised by techniques for memory access
- H03M 7/4075: {Golomb codes}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

## Claims

### Claim 1

A method of converting, in hardware, an input number to an output m-bit number, the method comprising:
determining, in a truncation unit, an intermediate m-bit number; and
generating the output m-bit number by adding an adjustment value to the intermediate m-bit number.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising setting the adjustment value, wherein setting the adjustment value comprises:
for each of a plurality of pre-determined subsets of the bits of the input number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

### Claim 3

A method of converting, in hardware, an input number to an output m-bit number, the method comprising:
determining, in a replication unit, an intermediate m-bit number; and
generating the output m-bit number by adding an adjustment value to the intermediate m-bit number.

### Claim 4 (depends on 3)

The method according to claim 3, wherein n is a number of bits in the input number, and further wherein if m>2n, determining an intermediate m-bit number comprises:
appending (k−1) repetitions of the input number to the input number followed by r most significant bits of the input number, where k=└(m/n)┘ and r=m mod n.

### Claim 5 (depends on 3)

The method according to claim 3, further comprising setting the adjustment value, wherein setting the adjustment value comprises:
for each of a plurality of pre-determined subsets of the bits of the input number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

### Claim 6 (depends on 1)

The method of claim 1, wherein the method is used in a method of frame buffer compression.

### Claim 7 (depends on 6)

The method of claim 6, wherein the method of frame buffer compression further comprises:
storing one or more bits of pixel data in a frame buffer; and
outputting the stored one or more bits of pixel data to a display.

### Claim 8

Hardware logic arranged to convert, in hardware, an input number to an output m-bit number, the hardware logic comprising:
a truncation unit arranged to determine an intermediate m-bit number; and
an addition unit arranged to add an adjustment value to the intermediate m-bit number to generate the output m-bit number.

### Claim 9 (depends on 1)

Hardware logic configured to perform the method of claim 1, optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

### Claim 10 (depends on 3)

Hardware logic configured to perform the method of claim 3, optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

### Claim 11 (depends on 8)

A data compression unit comprising the hardware logic according to claim 8.

### Claim 12 (depends on 9)

A data compression unit comprising the hardware logic according to claim 9.

### Claim 13 (depends on 10)

A data compression unit comprising the hardware logic according to claim 10.

### Claim 14 (depends on 1)

A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 1.

### Claim 15 (depends on 3)

A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 3.

### Claim 16 (depends on 8)

A method of manufacturing hardware logic as set forth in claim 8, comprising using an integrated circuit manufacturing system.

### Claim 17 (depends on 8)

An integrated circuit definition dataset embodied in a non-transitory storage medium that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture hardware logic as set forth in claim 8.

### Claim 18 (depends on 8)

A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture hardware logic as set forth in claim 8.

### Claim 19 (depends on 8)

An integrated circuit manufacturing system configured to manufacture hardware logic as set forth in claim 8.

### Claim 20 (depends on 8)

An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes hardware logic as set forth in claim 8;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the hardware logic; and
an integrated circuit generation system configured to manufacture the hardware logic according to the circuit layout description.