# US 2022/0286138 A1 · Phase Locked Loop with Low Reference Spur

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- Number: US 2022/0286138 A1
- Document ID: US20220286138A1
- Status: Published application
- Kind: A1
- Application number: 17/191,268
- Filed: 2021-03-03
- Published: 2022-09-08
- Earliest claimed: 2021-03-03
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corp.
- Inventors: Chun-Ju Shen; Ying Wei; Vishnu Balan
- Web page: https://patentgrep.com/patent/US20220286138A1

## CPC

- H03L 7/0893: {the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop}
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A calibration circuit including multiple charge pumps supplying a voltage controlled oscillator along different paths, one path being an integration path from a first one of the charge pumps to the voltage controlled oscillator, and one path being a proportional path from a second one of the charge pumps to the voltage controlled oscillator. A phase locked loop of the calibration circuit utilizes a switch capacitor circuit to reduce reference spur and improve the accuracy of clock edges for multi-phase calibration.

## Claims

### Claim 1

A circuit comprising:
a plurality of charge pumps;
a voltage controlled oscillator;
an integration path from a first one of the charge pumps to the voltage controlled oscillator; and
a proportional path from a second one of the charge pumps to the voltage controlled oscillator.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the proportional path comprises a switched capacitive circuit.

### Claim 3 (depends on 2)

The circuit of claim 2, the switched capacitive circuit comprising:
a plurality of reset switches;
a plurality of sample switches; and
a plurality of hold switches.

### Claim 4 (depends on 2)

The circuit of claim 2, wherein the switched capacitive circuit comprises a parallel configuration of sample and hold switches.

### Claim 5 (depends on 2)

The circuit of claim 2, further comprising:
a reset-sample-hold circuit configured to control the switched capacitive circuit.

### Claim 6 (depends on 1)

The circuit of claim 1, further comprising:
a first voltage-to-current converter configured on the integration path; and
a second voltage-to-current converter configured on the proportional path.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein outputs of the first voltage-to-current converter and the second voltage-to-current converter are merged into a current controlled oscillator.

### Claim 8

A phase locked loop comprising:
a first charge pump;
a second charge pump;
a voltage controlled oscillator;
a first path dominated by capacitive effects from the first charge pump to the voltage controlled oscillator;
a second path dominated by resistive effects from the second charge pump to the voltage controlled oscillator; and
the charge pumps configured to output different valued currents on the first path and the second path during operation of the circuit.

### Claim 9 (depends on 8)

The phase locked loop of claim 8, wherein the first path comprises a switched capacitive circuit.

### Claim 10 (depends on 9)

The phase locked loop of claim 9, the switched capacitive circuit comprising a plurality of sample switches shunted by a plurality of reset switches.

### Claim 11 (depends on 9)

The phase locked loop of claim 9, wherein the switched capacitive circuit comprises an inner node coupled to a reference voltage comparator.

### Claim 12 (depends on 9)

The phase locked loop of claim 9, further comprising:
a reset-sample-hold circuit configured to control the switched capacitive circuit.

### Claim 13 (depends on 8)

The phase locked loop of claim 8, further comprising:
a first voltage-to-current converter configured on the first path; and
a second voltage-to-current converter configured on the second path.

### Claim 14 (depends on 13)

The phase locked loop of claim 13, wherein outputs of the first voltage-to-current converter and the second voltage-to-current converter are combined at an input of a current controlled oscillator.

### Claim 15

A transceiver comprising:
a data transmitting circuit;
a data receiving circuit coupled to receive data signals from the transmitting circuit;
one or more clock signal generators coupled to one or both of the transmitting circuit and the receiving circuit;
one or more clock calibration circuits coupled to the one or more clock signal generators, at least one of the clock calibration circuits comprising:
a plurality of charge pumps; and
a voltage controlled oscillator configured to receive current from both of an integration path from a first one of the charge pumps and a proportional path from a second one of the charge pumps.

### Claim 16 (depends on 15)

The transceiver of claim 15, wherein the proportional path comprises a switched capacitive circuit.

### Claim 17 (depends on 16)

The transceiver of claim 16, the switched capacitive circuit comprising a series-parallel configuration of switches.

### Claim 18 (depends on 16)

The transceiver of claim 16, further comprising:
a reset-sample-hold circuit configured to control the switched capacitive circuit.

### Claim 19 (depends on 15)

The transceiver of claim 15, further comprising:
a first gain circuit configured on the integration path; and
a second gain circuit configured on the proportional path.

### Claim 20 (depends on 19)

The transceiver of claim 19, wherein outputs of the first gain circuit and the second gain circuit are merged.