# US 2022/0286129 A1 · Trap circuits for use with capacitively-coupled resonant clock networks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0286129 A1 - Document ID: US20220286129A1 - Status: Published application - Kind: A1 - Application number: 17/669,502 - Filed: 2022-02-11 - Published: 2022-09-08 - Earliest claimed: 2021-03-08 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Bouchaib CHERIF; Max Earl NIELSEN - Web page: https://patentgrep.com/patent/US20220286129A1 ## CPC - H03K 17/92: by the use, as active elements, of superconductive devices - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03K 19/195: using superconductive devices - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ. ## Claims ### Claim at position 1 -20. (canceled) ### Claim 21 A superconducting integrated circuit comprising: a clock line coupled: (1) to a first Josephson junction via a first capacitor, wherein the first capacitor is configured to receive a clock signal via the clock line and couple a first bias current to the first Josephson junction, and (2) to a second Josephson junction via a second capacitor, wherein the second capacitor is configured to receive a clock signal via the clock line and couple a second bias current to the second Josephson junction; and a trap circuit coupled between the first capacitor and the first Josephson junction, wherein the trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and any other Josephson junctions capacitively-coupled to the clock line, including the second Josephson junction. ### Claim 22 (depends on 21) The superconducting integrated circuit of claim 21, wherein the trap circuit comprises a trap capacitor coupled in parallel with a trap inductor to form an LC tank. ### Claim 23 (depends on 22) The superconducting integrated circuit of claim 22, wherein the trap circuit further comprises a damping resistor coupled in parallel to the LC tank. ### Claim 24 (depends on 21) The superconducting integrated circuit of claim 21, further comprising a damping resistor coupled to a node between the trap circuit and a ground terminal. ### Claim 25 (depends on 21) The superconducting integrated circuit of claim 21, wherein the clock line corresponds to a capacitively-coupled resonant clock network. ### Claim 26 (depends on 21) The superconducting integrated circuit of claim 21, wherein the clock signal comprises an alternating current clock signal configured to supply power to any superconducting circuits coupled to the clock line. ### Claim 27 (depends on 21) The superconducting integrated circuit of claim 21, wherein the first Josephson junction has a plasma frequency, and wherein the trap circuit is configured to attenuate at least any signals having a frequency in a range between 0.8 times the plasma frequency to 1.2 times the plasma frequency. ### Claim 28 A superconducting integrated circuit comprising: a resonant clock network capacitively-coupled to a first Josephson junction and a second Josephson junction; and a trap circuit coupled between the first Josephson junction and the resonant clock network, wherein the trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and any other Josephson junctions capacitively-coupled to the resonant clock network, including the second Josephson junction. ### Claim 29 (depends on 28) The superconducting integrated circuit of claim 28, wherein the trap circuit comprises a trap capacitor coupled in parallel with a trap inductor to form an LC tank. ### Claim 30 (depends on 29) The superconducting integrated circuit of claim 29, wherein the trap circuit further comprises a damping resistor coupled in parallel to the LC tank. ### Claim 31 (depends on 28) The superconducting integrated circuit of claim 28, further comprising a damping resistor coupled to a node between the trap circuit and a ground terminal. ### Claim 32 (depends on 28) The superconducting integrated circuit of claim 28, wherein the resonant clock network comprises metamaterial transmission lines configured to supply a clock signal to any superconducting circuits coupled to the resonant clock network. ### Claim 33 (depends on 32) The superconducting integrated circuit of claim 32, wherein the clock signal comprises an alternating current clock signal configured to supply power to any superconducting circuits coupled to the resonant clock network. ### Claim 34 (depends on 28) The superconducting integrated circuit of claim 28, wherein the first Josephson junction has a plasma frequency, and wherein the trap circuit is configured to attenuate at least any signals having a frequency in a range between 0.8 times the plasma frequency to 1.2 times the plasma frequency. ### Claim 35 A superconducting integrated circuit comprising: a first capacitor for coupling a first Josephson junction to a first node of a first clock line associated with the resonant clock network, wherein the first clock line is configured to provide a first clock signal having a first phase; a second capacitor for coupling a second Josephson junction to a second node of the first clock line; a third capacitor for coupling a third Josephson junction to a first node of a second clock line associated with the resonant clock network, wherein the second clock line is configured to provide a second clock signal having a second phase different from the first phase; a fourth capacitor for coupling a fourth Josephson junction to a second node of the second clock line; a first trap circuit coupled between the first capacitor and the first Josephson junction, wherein the first trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and any other Josephson junctions capacitively-coupled to the first clock line, including the second Josephson junction; and a second trap circuit coupled between the third capacitor and the third Josephson junction, wherein the second trap circuit is configured to attenuate any signals generated by a triggering of the third Josephson junction to reduce crosstalk between the third Josephson junction and any other Josephson junctions capacitively-coupled to the second clock line, including the fourth Josephson junction. ### Claim 36 (depends on 35) The superconducting integrated circuit of claim 35, wherein the first trap circuit comprises a first trap capacitor coupled in parallel with a first trap inductor to form a first LC tank, and wherein the second trap circuit comprises a second trap capacitor coupled in parallel with a second trap inductor to form a second LC tank. ### Claim 37 (depends on 36) The superconducting integrated circuit of claim 36, wherein the first trap circuit further comprises a first damping resistor coupled in parallel to the first LC tank, and wherein the second trap circuit further comprises a second damping resistor coupled in parallel to the second LC tank. ### Claim 38 (depends on 35) The superconducting integrated circuit of claim 35, further comprising a first damping resistor coupled to a first node between the first trap circuit and a ground terminal, and a second damping resistor coupled to a second node between the second trap circuit and the ground terminal. ### Claim 39 (depends on 35) The superconducting integrated circuit of claim 35, wherein the first clock signal comprises a first alternating current clock signal configured to supply power to any superconducting circuits coupled to the first clock line, and wherein the second clock signal comprises a second alternating current clock signal configured to supply power to any superconducting circuits coupled to the second clock line. ### Claim 40 (depends on 35) The superconducting integrated circuit of claim 35, wherein the first Josephson junction has a first plasma frequency, and wherein the first trap circuit is configured to attenuate at least any signals having a first frequency in a range between 0.8 times the first plasma frequency to 1.2 times the first plasma frequency, and wherein the third Josephson junction has a second plasma frequency, and wherein the second trap circuit is configured to attenuate at least any signals having a second frequency in a range between 0.8 times the second plasma frequency to 1.2 times the second plasma frequency.