Input buffer circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Kai TSAI, Chia-Hui CHEN, Chia-Jung CHANG
Life of this patent
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Abstract
An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.
Claims22
An integrated circuit comprising:
- an upper threshold circuit configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage;
- a first switch electrically connected between an upper supply voltage and a buffer output node, wherein the first switch is configured to be controlled by the first enabling signal;
- a lower threshold circuit configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage;
- a second switch electrically connected between the buffer output node and a lower supply voltage, wherein the second switch is configured to be controlled by the second enabling signal;
- and
- a control circuit configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.
(canceled)
The integrated circuit of claim 10, wherein the control circuit further comprises a regenerative circuit electrically coupled to the buffer output node.
A method comprising:
- generating a first enabling signal based comparing an input voltage signal with an upper threshold voltage;
- controlling a first switch with the first enabling signal, wherein the first switch is electrically connected between an upper supply voltage and a buffer output node;
- generating a second enabling signal based on comparing the input voltage signal with a lower threshold voltage;
- controlling a second switch with the second enabling signal, wherein the second switch is electrically connected between the buffer output node and a lower supply voltage;
- changing an output voltage signal from a first voltage level to a second voltage level when each of the first enabling signal and the second enabling signal changes a logical level consecutively.
(canceled)
An integrated circuit comprising:
- an upper threshold circuit configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage;
- a lower threshold circuit configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage;
- a first switch electrically connected between an upper supply voltage and a buffer output node and configured to receive the first enabling signal from the upper threshold circuit;
- and
- a second switch electrically connected between the buffer output node and a lower supply voltage and configured to receive the second enabling signal from the lower threshold circuit.
Dependencies are inferred from the claim text.