# US 2022/0285533 A1 · Multi-gate device and related methods

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0285533 A1
- Document ID: US20220285533A1
- Status: Published application
- Kind: A1
- Application number: 17/465,762
- Filed: 2021-09-02
- Published: 2022-09-08
- Earliest claimed: 2021-03-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tsung-Lin LEE; Choh Fei YEAP; Da-Wen LIN; Chih-Chieh YEH
- Web page: https://patentgrep.com/patent/US20220285533A1

## CPC

- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/679: {comprising air gaps}
- H10P 14/3452: {Microstructure}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
providing a fin extending from a substrate, wherein the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers;
removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers;
after forming the trench, performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench; and
conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

### Claim 2 (depends on 1)

The method of claim 1, wherein the cap layer includes a silicon (Si) layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the cap layer includes a first material composition that is the same as a second material composition of the plurality of semiconductor channel layers.

### Claim 4 (depends on 1)

The method of claim 1, wherein the cap layer increases an effective thickness of the plurality of semiconductor channel layers in a lightly-doped drain (LDD) region of the semiconductor device.

### Claim 5 (depends on 1)

The method of claim 1, wherein the dummy layer recess process consumes a first thickness of the plurality of semiconductor channel layers in a lightly-doped drain (LDD) region of the semiconductor device, and wherein the cap layer has a second thickness that is less than or equal to the first thickness.

### Claim 6 (depends on 1)

The method of claim 1, wherein a ratio of thicknesses between a semiconductor channel layer of the plurality of semiconductor channel layers and a dummy layer of the plurality of dummy layers is in a range of between about ½ and ⅕.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
after forming the cap layer, forming an inner spacer over the cap layer within the first recesses, wherein the cap layer formed on the lateral surfaces of the semiconductor channel layers remains exposed; and
after forming the inner spacer, epitaxially growing a source/drain feature in the source/drain region.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
after forming the inner spacer and prior to epitaxially growing the source/drain feature, performing a lateral sheet trim process that etches both the cap layer on the lateral surfaces of the plurality of semiconductor channel layers and ends of the plurality of semiconductor channel layers to form second recesses along the sidewall of the trench.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
after epitaxially growing the source/drain feature, performing a channel release process to remove the plurality of dummy layers and form gaps between adjacent semiconductor channel layers of the plurality of semiconductor channel layers; and
forming at least a portion of a gate structure within the gaps.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
after performing the channel release process and prior to forming the portion of the gate structure within the gaps, performing a sheet trim process to remove portions of top and bottom surfaces of each of the plurality of semiconductor channel layers in a channel region of the semiconductor device, wherein after the sheet trim process, an effective thickness of the plurality of semiconductor channel layers in a lightly-doped drain (LDD) region of the semiconductor device is greater than a thickness of the plurality of semiconductor channel layers in the channel region of the semiconductor device.

### Claim 11

A method, comprising:
providing a fin structure including epitaxial layers of a first composition interposed by epitaxial layers of a second composition, wherein the epitaxial layers of the first composition are at least twice as thick as the epitaxial layers of the second composition;
forming a dummy gate over the fin structure and a spacer layer on sidewalls of the dummy gate;
etching lateral ends of the epitaxial layers of the first composition to form recesses, the recesses disposed beneath the spacer layer and between adjacent epitaxial layers of the second composition; and
forming a silicon (Si) cap layer on opposing ends of the epitaxial layers of the second composition and within the recesses.

### Claim 12 (depends on 11)

The method of claim 11, wherein a region of the epitaxial layers of the second composition disposed beneath the spacer layer includes a lightly-doped drain (LDD) region, and wherein the Si cap layer increases an effective thickness of the epitaxial layers of the second composition in the LDD region.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
after forming the Si cap layer, forming an inner spacer on the cap layer within the recesses; and
after forming the inner spacer, forming a source/drain feature in a source/drain region adjacent to the dummy gate.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
after forming the inner spacer and prior to forming the source/drain feature, etching both the Si cap layer on the opposing ends of the epitaxial layers of the second composition and ends of the epitaxial layers of the second composition reduce a distance between the source/drain feature and a channel region of the epitaxial layer of the second composition.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
after forming the source/drain feature, removing both the dummy gate and the epitaxial layers of the first composition to form gaps between adjacent epitaxial layers of the epitaxial layers of the second composition; and
forming a high-K/metal gate stack within the gaps.

### Claim 16 (depends on 15)

The method of claim 15, wherein the removing the epitaxial layers of the first composition also removes portions of top and bottom surfaces of each of the epitaxial layers of the second composition in a channel region such that a channel region thickness of the epitaxial layers of the second composition is less than a lightly-doped drain (LDD) region thickness of the epitaxial layers of the second composition.

### Claim 17

A semiconductor device, comprising:
a fin extending from a substrate, wherein the fin includes a plurality of semiconductor channel layers, and wherein each semiconductor channel layer of the plurality of semiconductor channel layers includes a channel region and a lightly-doped drain (LDD) region;
a cap layer surrounding the LDD region of each semiconductor channel layer of the plurality of semiconductor channel layers; and
inner spacers disposed between first portions of the cap layer disposed in the LDD region of adjacent semiconductor channel layers of the plurality of semiconductor channel layers;
wherein a first thickness of the plurality of semiconductor channel layers in the LDD region combined with a second thickness of the cap layer provides an effective thickness of the plurality of semiconductor channel layers in the LDD region, and wherein the effective thickness is greater than a third thickness of the plurality of semiconductor channel layers in the channel region.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a portion of a gate structure disposed between channel regions of adjacent semiconductor channel layers of the plurality of semiconductor channel layers, wherein the inner spacers are further disposed on either side of the portion of the gate structure; and
source/drain features disposed on either side of the gate structure and in contact with second portions of the cap layer disposed on lateral surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the cap layer includes a silicon (Si) layer.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, further including a void disposed between the source/drain features and at least one adjacent inner spacer.