# US 2022/0285489 A1 · Super junction silicon carbide semiconductor device and manufacturing method thereof

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- Number: US 2022/0285489 A1
- Document ID: US20220285489A1
- Status: Published application
- Kind: A1
- Application number: 17/685,930
- Filed: 2022-03-03
- Published: 2022-09-08
- Earliest claimed: 2021-03-08
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Kensuke TAKENAKA; Takeshi TAWARA; Shinsuke HARADA
- Web page: https://patentgrep.com/patent/US20220285489A1

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 12/031: {of IGBTs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/052: {by forming stacked epitaxial layers}
- H10D 62/054: {by high energy implantations in bulk semiconductor bodies, e.g. forming pillars}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/8325: {Silicon carbide}
- H10D 12/032: {of vertical IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

## Claims

### Claim 1

A method of manufacturing a superjunction silicon carbide semiconductor device, the method comprising:
as a first process, forming a parallel pn structure on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, the parallel pn structure having a plurality of first columns of the first conductivity type and a plurality of second columns of a second conductivity type, the first columns and the second columns being disposed repeatedly alternating one another in a plane parallel to the front surface;
as a second process, forming a first semiconductor layer of the second conductivity type at a surface of the parallel pn structure;
as a third process, selectively forming a plurality of first semiconductor regions of the first conductivity type in a surface layer of the first semiconductor layer;
as a fourth process, forming a gate insulating film in contact with the first semiconductor layer;
as a fifth process, forming a gate electrode on a first surface of the gate insulating film, the first surface being opposite to a second surface of the gate insulating film, the second surface being in contact with the first semiconductor layer;
as a sixth process, forming a first electrode in contact with the first semiconductor layer and the first semiconductor regions; and
as a seventh process, forming a second electrode on a back surface of the silicon carbide semiconductor substrate, wherein
in the first process, forming an epitaxial layer of the second conductivity type on the front surface of the silicon carbide semiconductor substrate and selectively forming a plurality of semiconductor regions of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated a plurality of times, thereby forming the parallel pn structure.

### Claim 2 (depends on 1)

The method according to claim 1, wherein
an acceleration energy when the nitrogen ions are implanted is in a range of 10 keV to 50 MeV.

### Claim 3 (depends on 1)

The method according to claim 1, further comprising after the third process but before the fourth process
as an eighth process, forming a plurality of trenches that penetrate through the first semiconductor layer and the first semiconductor regions and reach the first columns, wherein
in the fourth process, the gate insulating film is formed in each of the trenches, and
in the fifth process, the gate electrode is formed in each of the trenches via the gate insulating film.