# US 2022/0285488 A1 · Superjunction semiconductor device having floating region and method of manufacturing same

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- Number: US 2022/0285488 A1
- Document ID: US20220285488A1
- Status: Published application
- Kind: A1
- Application number: 17/584,891
- Filed: 2022-01-26
- Published: 2022-09-08
- Earliest claimed: 2021-03-03
- Assignees: DB HiTek Co., Ltd.
- Applicants: DB HiTek Co., Ltd.
- Inventors: Myeong Bum PYUN; Won Kook CHO
- Web page: https://patentgrep.com/patent/US20220285488A1

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 62/054: {by high energy implantations in bulk semiconductor bodies, e.g. forming pillars}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed are a superjunction semiconductor device having a floating region and a method of manufacturing the same. More particularly, a superjunction semiconductor device having a floating region and a method of manufacturing the same are disclosed, in which a floating region including first conductivity type impurities is between adjacent pillars in a ring region, so that an electric field can easily expand in the ring region under an N-rich condition, thereby improving breakdown voltage (BV) characteristics and ensuring device stability.

## Claims

### Claim 1

A superjunction semiconductor device, comprising:
a substrate;
first and second epitaxial layers on the substrate, the first epitaxial layer in a cell region and the second epitaxial layer in a ring region;
a plurality of pillars spaced apart from each other in a transverse direction in the first epitaxial layer and the second epitaxial layer;
a body region on each of the pillars in the first epitaxial layer;
a source in the body region;
a gate electrode on the first epitaxial layer; and
a floating region in the second epitaxial layer between adjacent pillars in the ring region.

### Claim 2 (depends on 1)

The superjunction semiconductor device of claim 1, wherein the floating region has substantially a same doping concentration as the pillars.

### Claim 3 (depends on 1)

The superjunction semiconductor device of claim 1, wherein the floating region has a predetermined length in a longitudinal direction in the ring region.

### Claim 4 (depends on 3)

The superjunction semiconductor device of claim 3, wherein the predetermined length of the floating region is less than that of the adjacent pillars along the longitudinal direction in the ring region.

### Claim 5 (depends on 1)

The superjunction semiconductor device of claim 1, wherein the floating region is in the ring region at a position adjacent to the cell region.

### Claim 6 (depends on 5)

The superjunction semiconductor device of claim 5, wherein the floating region has an end thereof adjacent to or in contact with a boundary between the ring region and the cell region.

### Claim 7

A superjunction semiconductor device, comprising:
a substrate;
a second conductivity type epitaxial layer on the substrate, including a first epitaxial layer in a cell region and a second epitaxial layer in a ring region;
a plurality of first conductivity type pillars alternating with portions of the epitaxial layer, spaced apart from each other in a transverse direction in the first epitaxial layer and the second epitaxial layer;
a first conductivity type body region on each of the pillars in the first epitaxial layer;
a second conductivity type source in the body region;
a gate electrode on the first epitaxial layer; and
a floating region in the second epitaxial layer between adjacent pillars in the ring region,
wherein the floating region has an uppermost surface substantially flush with uppermost surfaces of the adjacent pillars and a vertical thickness or height equal to or less than half of that of the adjacent pillars.

### Claim 8 (depends on 7)

The superjunction semiconductor device of claim 7, wherein the floating region has a dose ratio of P-type to N-type impurities equal to or less than 1.

### Claim 9 (depends on 7)

The superjunction semiconductor device of claim 7, further comprising:
a body contact in the body region adjacent to or in contact with the source; and
a gate oxide layer between the gate electrode and the first epitaxial layer.

### Claim 10 (depends on 9)

The superjunction semiconductor device of claim 9, wherein the floating region is between the adjacent pillars in the ring region adjacent to the cell region, and
the floating region has a length in the longitudinal direction less than that of the adjacent pillars in the longitudinal direction.

### Claim 11 (depends on 89)

The superjunction semiconductor device of claim 89, wherein the floating region is in a ring Y region or a ring corner region.

### Claim 12

A method of manufacturing a superjunction semiconductor device, the method comprising:
forming a first epitaxial layer and a second epitaxial layer on a substrate;
forming a plurality of pillars in the epitaxial layer, spaced apart from each other in a transverse direction;
forming a gate oxide layer on the first epitaxial layer;
forming a gate electrode on the gate oxide layer; and
forming a floating region between adjacent pillars in the second epitaxial layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the floating region is formed at a position corresponding to upper portions of the adjacent pillars.

### Claim 14 (depends on 12)

The method of claim 12, wherein the floating region and the pillars are formed contemporaneously.

### Claim 15 (depends on 14)

The method of claim 14, wherein an uppermost surface of the floating region is substantially flush with uppermost surfaces of the adjacent pillars, and a vertical thickness or height of the floating region is less than that of the adjacent pillars.

### Claim 16 (depends on 14)

The method of claim 14, wherein a length of the floating region in a longitudinal direction is less than that of the adjacent pillars in the longitudinal direction in a ring region.

### Claim 17

A method of manufacturing a superjunction semiconductor device, the method comprising:
forming a second conductivity type epitaxial layer including a first epitaxial layer and a second epitaxial layer on a substrate;
forming a plurality of first conductivity type pillars in the epitaxial layer, spaced apart from each other in a transverse direction;
forming a gate oxide layer on the first epitaxial layer;
forming a gate electrode on the gate oxide layer; and
forming a first conductivity type floating region between adjacent pillars in the second epitaxial layer,
wherein the floating region is adjacent to a cell region and has a dose ratio of P-type to N-type impurities equal to or less than 1.

### Claim 18 (depends on 17)

The method of claim 17, wherein the floating region has a predetermined length equal to or less than half of that of the adjacent pillars, an uppermost surface of the floating region is substantially flush with uppermost surfaces of the adjacent pillars, and a vertical thickness or height of the floating region is equal to or less than half of that of the adjacent pillars.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
forming a second conductivity type source in each body region; and
forming a first conductivity type body contact adjacent to or in contact with the source.

### Claim 20 (depends on 19)

The method of claim 19, wherein the body contact is formed in a center of the source, thereby separating the source into two source regions in the transverse direction.