# US 2022/0285409 A1 · Passivation scheme for image sensor substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285409 A1 - Document ID: US20220285409A1 - Status: Published application - Kind: A1 - Application number: 17/340,458 - Filed: 2021-06-07 - Published: 2022-09-08 - Earliest claimed: 2021-03-05 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Kai-Yun Yang - Web page: https://patentgrep.com/patent/US20220285409A1 ## CPC - H10F 39/807: {Pixel isolation structures} - H10F 39/016: {of thin-film-based image sensors} - H10F 39/028: {performed after manufacture of the image sensors, e.g. annealing, gettering of impurities, short-circuit elimination or recrystallisation} - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract The present disclosure relates to an integrated chip including a substrate. A photodetector is arranged within the substrate. A trench isolation structure extends into the substrate on opposite sides of the photodetector. The trench isolation structure separates the photodetector from neighboring photodetectors. A first passivation layer is between a sidewall of the substrate and a sidewall of the trench isolation structure. The first passivation layer includes hydrogenated amorphous silicon. ## Claims ### Claim 1 An integrated chip, comprising: a substrate; a photodetector arranged within the substrate; a trench isolation structure extending into the substrate on opposite sides of the photodetector, wherein the trench isolation structure separates the photodetector from neighboring photodetectors; and a first passivation layer between a sidewall of the substrate and a sidewall of the trench isolation structure, wherein the first passivation layer comprises hydrogenated amorphous silicon. ### Claim 2 (depends on 1) The integrated chip of claim 1, wherein the first passivation layer is on the sidewall of the substrate and on the sidewall of the trench isolation structure. ### Claim 3 (depends on 1) The integrated chip of claim 1, wherein the first passivation layer is on the sidewall of the substrate, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the integrated chip further comprises: a second passivation layer on the first passivation layer and on the sidewall of the trench isolation structure, wherein the second passivation layer comprises hydrogenated amorphous silicon that has p-type doping. ### Claim 4 (depends on 1) The integrated chip of claim 1, wherein the first passivation layer is on the sidewall of the substrate, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the integrated chip further comprises: a second passivation layer on the first passivation layer, wherein the second passivation layer comprises hydrogenated amorphous silicon that has p-type doping; and a third passivation layer on the second passivation layer and on the sidewall of the trench isolation structure, wherein the third passivation layer comprises aluminum oxide. ### Claim 5 (depends on 1) The integrated chip of claim 1, wherein the hydrogenated amorphous silicon has p-type doping and the substrate has n-type doping along the sidewall of the substrate. ### Claim 6 (depends on 1) The integrated chip of claim 1, wherein the hydrogenated amorphous silicon has p-type doping and the substrate has p-type doping along the sidewall of the substrate, and wherein a p-type dopant concentration of the hydrogenated amorphous silicon is greater than a p-type dopant concentration of the substrate. ### Claim 7 (depends on 1) The integrated chip of claim 1, wherein the substrate comprises a first semiconductor well having a first doping type and a second semiconductor well having a second doping type opposite the first doping type, wherein the first semiconductor well extends from a first sidewall of the first passivation layer to a second sidewall of the first passivation layer, opposite the first sidewall, and wherein a bottom surface of the first passivation layer is on a top of the second semiconductor well. ### Claim 8 (depends on 1) The integrated chip of claim 1, wherein the substrate comprises crystalline silicon, wherein a hydrogen concentration of the hydrogenated amorphous silicon is between 4% and 35%, and wherein a p-type dopant concentration of the hydrogenated amorphous silicon is between 1014 cm−3 and 1021 cm−3. ### Claim 9 An integrated chip, comprising: a substrate; a first semiconductor well within the substrate, wherein the first semiconductor well forms a photodetector within the substrate; a trench isolation structure extending into the first semiconductor well on opposite sides of the photodetector, wherein the trench isolation structure separates the photodetector from neighboring photodetectors; and a passivation structure between the first semiconductor well and the trench isolation structure, wherein the first semiconductor well is on a sidewall of the passivation structure, wherein the passivation structure is on a sidewall of the trench isolation structure, and wherein the passivation structure comprises hydrogenated amorphous silicon. ### Claim 10 (depends on 9) The integrated chip of claim 9, wherein the passivation structure consists of a first passivation layer that comprises the hydrogenated amorphous silicon, wherein the hydrogenated amorphous silicon has p-type doping, wherein the first semiconductor well is on a sidewall of the first passivation layer, and wherein the first passivation layer is on the sidewall of the trench isolation structure. ### Claim 11 (depends on 9) The integrated chip of claim 9, wherein the passivation structure consists of a first passivation layer and a second passivation layer over the first passivation layer, wherein the first semiconductor well is on a sidewall of the first passivation layer, wherein the first passivation layer comprises intrinsic hydrogenated amorphous silicon, and wherein the second passivation layer is on the sidewall of the trench isolation structure and comprises p-type hydrogenated amorphous silicon. ### Claim 12 (depends on 9) The integrated chip of claim 9, wherein the passivation structure consists of a first passivation layer, a second passivation layer over the first passivation layer, and a third passivation layer over the second passivation layer, wherein the first semiconductor well is on a sidewall of the first passivation layer, wherein the first passivation layer comprises intrinsic hydrogenated amorphous silicon, wherein the second passivation layer comprises p-type hydrogenated amorphous silicon, and wherein the third passivation layer is on the sidewall of the trench isolation structure and comprises aluminum oxide. ### Claim 13 (depends on 9) The integrated chip of claim 9, wherein the passivation structure consists of a first passivation layer and a second passivation layer over the first passivation layer, wherein the first semiconductor well is on a sidewall of the first passivation layer, wherein the first passivation layer comprises p-type hydrogenated amorphous silicon, and wherein the second passivation layer is on the sidewall of the trench isolation structure and comprises aluminum oxide. ### Claim 14 (depends on 9) The integrated chip of claim 9, wherein the first semiconductor well has a first doping type, and wherein the integrated chip further comprises: a second semiconductor well within the substrate, the second semiconductor well having a second doping type opposite the first doping type, wherein the second semiconductor well is directly below the trench isolation structure, and wherein the passivation structure extends between the trench isolation structure and the second semiconductor well. ### Claim 15 (depends on 14) The integrated chip of claim 14, wherein a bottom surface of the passivation structure is below a top of the second semiconductor well, wherein the second semiconductor well extends along the sidewall of the passivation structure, and wherein the top of the second semiconductor well is below a top surface of the passivation structure. ### Claim 16 A method for forming an integrated chip, the method comprising: forming a photodetector in a substrate; patterning the substrate to form a trench in the substrate, wherein the trench is formed by sidewalls of the substrate, and wherein the trench surrounds the photodetector; depositing a first passivation layer on the sidewalls of the substrate that form the trench, the first passivation layer comprising hydrogenated amorphous silicon; and depositing a dielectric layer over the first passivation layer and in a remainder of the trench to form a trench isolation structure over the first passivation layer and surrounding the photodetector. ### Claim 17 (depends on 16) The method of claim 16, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the method further comprises: depositing a second passivation layer over the first passivation layer, the second passivation layer comprising hydrogenated amorphous silicon that has p-type doping. ### Claim 18 (depends on 17) The method of claim 17, further comprising: depositing a third passivation layer over the second passivation layer, the third passivation layer comprising aluminum oxide. ### Claim 19 (depends on 17) The method of claim 17, further comprising: annealing the first passivation layer at a temperature of less than 250 degrees Celsius. ### Claim 20 (depends on 17) The method of claim 17, wherein depositing the first passivation layer results in the first passivation layer being disposed along a backside of the substrate, wherein depositing the dielectric layer results in the dielectric layer being disposed along the backside of the substrate, and wherein the method further comprises: performing a planarization process on the dielectric layer and the first passivation layer to remove the dielectric layer and the first passivation layer from along the backside of the substrate.