# US 2022/0285387 A1 · Three-dimensional memory device including laterally-undulating memory material layers and methods for forming the same

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- Number: US 2022/0285387 A1
- Document ID: US20220285387A1
- Status: Published application
- Kind: A1
- Application number: 17/192,603
- Filed: 2021-03-04
- Published: 2022-09-08
- Earliest claimed: 2021-03-04
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Tatsuya HINOUE; Zhixin CUI
- Web page: https://patentgrep.com/patent/US20220285387A1

## CPC

- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer.

## Claims

### Claim 1

A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel, a memory material layer having a laterally-undulating vertical cross-sectional profile and laterally surrounding the vertical semiconductor channel, and a vertical stack of insulating material portions which protrude from the insulating layers into the memory opening.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein each insulating material portion within the vertical stack of insulating material portions comprises a respective vertical cylindrical outer sidewall contacting or laterally spaced by a uniform distance from a respective one of the insulating layers, and a respective inner sidewall including at least one annular concave surface segment adjoined to a top edge or a bottom edge of the respective vertical cylindrical outer sidewall.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein for each insulating material portion except a topmost one and a bottommost one within the vertical stack of insulating material portions, the respective inner sidewall comprises:
a respective upper annular concave surface segment adjoined to the top edge of the respective vertical cylindrical outer sidewall and adjoined to a top edge of an inner cylindrical sidewall segment; and
a respective lower annular concave surface segment adjoined to the bottom edge of the respective vertical cylindrical outer sidewall and adjoined to a bottom edge of the inner cylindrical sidewall segment.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the insulating layers and the vertical stack of insulating material portions comprise a same insulating material.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the same insulating material comprises silicon oxide.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein portions of the memory material layer located at levels of the electrically conductive layers laterally protrude outward relative to portions of the memory material layer located at levels of the insulating layers from a vertical axis passing through a geometrical center of the memory opening fill structure.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the memory opening fill structure further comprises a blocking dielectric layer contacting an entirety of the inner sidewalls of the vertical stack of insulating material portions and contacting an entirety of an outer sidewall of the memory material layer.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein each of the electrically conductive layers is vertically spaced the memory opening fill structure and from an overlying one or an underlying one of the insulating layers by a respective backside blocking dielectric layer.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein one of the backside blocking dielectric layers contacts an upper portion of a cylindrical outer sidewall of one of the insulating material portions, a cylindrical segment of an outer sidewall of the blocking dielectric layer, and a lower portion of a cylindrical outer sidewall of another of the insulating material portions.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the respective vertical cylindrical outer sidewall of each insulating material portion contacts a cylindrical sidewall of the respective one of the insulating layers and a segment of a cylindrical sidewall of a respective one of the backside blocking dielectric layers.

### Claim 11 (depends on 7)

The memory device of claim 7, wherein the memory opening fill structure further comprises a vertical stack of metal oxide backside blocking dielectric portions located at levels of the electrically conductive layers and contacting segments of an outer sidewall of the blocking dielectric layer that are not in contact with the vertical stack of insulating material portions.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein each of the backside blocking dielectric portions has a shape having a vertical cross-sectional profile of a rectangle and contacts a cylindrical sidewall of a respective one of the electrically conductive layers.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the memory opening fill structure comprises a vertical stack of silicon oxide portions contacting an outer sidewall of a respective one of the insulating material portions and contacting a cylindrical sidewall of a respective one of the insulating layers and vertically interlaced with the vertical stack of backside blocking dielectric portions.

### Claim 14

A method of forming a semiconductor structure, comprising:
forming an alternating stack of sacrificial material layers and sacrificial material layers over a substrate;
forming a memory opening through the alternating stack;
forming lateral recesses at levels of the sacrificial material layers around the memory opening by laterally recessing the sacrificial material layers selective to the insulating layers around the memory opening;
forming a vertical stack of dielectric metal oxide portions in the lateral recesses;
forming a vertical stack of insulating material portions by selectively growing an insulating material at levels of sidewalls of the insulating layers within the memory opening while suppressing growth of the insulating material from physically exposed surfaces of the vertical stack of dielectric metal oxide portions;
forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises the vertical stack of dielectric metal oxide portions, the vertical stack of insulating material portions, a memory material layer and a vertical semiconductor channel that are sequentially formed over the vertical stack of insulating material portions; and
replacing the sacrificial material layers with electrically conductive layers.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the vertical semiconductor channel has a respective laterally-undulating vertical cross-sectional profile; and
the memory material layer is formed by a conformal deposition process, and has a laterally-undulating vertical cross-sectional profile providing outward lateral protrusions at levels of the sacrificial material layers from a vertical axis passing through a geometrical center of a volume of the memory opening.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
forming a backside trench through the alternating stack after formation of the memory opening fill structure;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers employing an isotropic etch process; and
depositing at least one conductive material in the backside recesses to form the electrically conductive layers.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the isotropic etch process is selective to the vertical stack of dielectric metal oxide portions;
the electrically conductive layers are formed directly on the vertical stack of dielectric metal oxide portions; and
the vertical stack of dielectric metal oxide portions comprise a vertical stack of backside blocking dielectric material portions.

### Claim 18 (depends on 16)

The method of claim 16, further comprising removing the vertical stack of dielectric metal oxide portions after formation of the backside recesses.

### Claim 19 (depends on 14)

The method of claim 14, wherein the step of forming the vertical stack of insulating material portions comprises selectively growing an insulating material directly from sidewalls of the insulating layers exposed in the memory opening.

### Claim 20 (depends on 14)

The method of claim 14, wherein the step of forming the vertical stack of insulating material portions comprises selectively growing an insulating material from an insulating material liner located on sidewalls of the insulating layers.