# US 2022/0285385 A1 · Memory device and method for fabricating the same

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- Number: US 2022/0285385 A1
- Document ID: US20220285385A1
- Status: Published application
- Kind: A1
- Application number: 17/190,576
- Filed: 2021-03-03
- Published: 2022-09-08
- Earliest claimed: 2021-03-03
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Erh-Kun LAI
- Web page: https://patentgrep.com/patent/US20220285385A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10B 43/40: characterised by the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stack disposed on the substrate, wherein the stack includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the upper surface of the substrate along a first direction; a channel layer penetrating the stack along the first direction, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction; and a memory layer disposed between the channel layer and the second conductive layer.

## Claims

### Claim 1

A memory device, comprising:
a substrate having an upper surface;
a stack disposed on the substrate, wherein the stack comprises a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the upper surface of the substrate along a first direction;
a channel layer penetrating the stack along the first direction, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction; and
a memory layer disposed between the channel layer and the second conductive layer.

### Claim 2 (depends on 1)

The memory device according to claim 1, further comprising a dielectric pillar, wherein the dielectric pillar penetrates the stack, and the channel layer surrounds the dielectric pillar.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein the channel layer is disposed between the dielectric pillar and the memory layer.

### Claim 4 (depends on 2)

The memory device according to claim 2, wherein the channel layer has an inner surface and an outer surface, the inner surface is opposite to the outer surface, and the inner surface contacts the dielectric pillar, and the outer surface contacts the memory layer.

### Claim 5 (depends on 1)

The memory device according to claim 1, wherein the channel layer is directly connected to the substrate.

### Claim 6 (depends on 1)

The memory device according to claim 1, further comprising a lower remnant portion disposed below the channel layer.

### Claim 7 (depends on 1)

The memory device according to claim 1, wherein a portion of the memory layer extends along the first direction and is disposed between the second conductive layer and the channel layer; other portions of the memory layer extend along a second direction and is disposed between the second conductive layer and the second insulating layer and between the second conductive layer and the third insulating layer, wherein the first direction and the second direction are intersected.

### Claim 8 (depends on 1)

The memory device according to claim 1, wherein the memory layer extends along the first direction and penetrates the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer.

### Claim 9 (depends on 1)

The memory device according to claim 1, further comprising an oxide layer disposed between the first conductive layer and the channel layer.

### Claim 10 (depends on 1)

The memory device according to claim 1, further comprising an oxide layer disposed between the first conductive layer and the memory layer.

### Claim 11

A method for fabricating a memory device, comprising:
providing a substrate, wherein the substrate has an upper surface;
forming a laminated body on the substrate, wherein the laminated body comprises a first insulating layer, a first conductive layer, a second insulating layer, a sacrificial layer and a third insulating layer along a first direction;
forming a first opening penetrating the laminated body;
forming a channel layer in the first opening, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction;
removing the sacrificial layer;
forming a second conductive layer at a position where the sacrificial layer is removed; and
forming a memory layer disposed between the channel layer and the second conductive layer.

### Claim 12 (depends on 11)

The method for fabricating the memory device according to claim 11, wherein the step of forming the channel layer further comprises:
forming an epitaxial growth layer covering the first opening by an epitaxial growth process;
removing a portion of the epitaxial growth layer to form a second opening, wherein a bottom surface of the second opening is higher than a top surface of the sacrificial layer;
forming a spacer on a sidewall of the second opening; and
removing the epitaxial growth layer not protected by the spacer to form a third opening exposing the substrate, and form the channel layer.

### Claim 13 (depends on 12)

The method for fabricating the memory device according to claim 12, further comprising:
filling the third opening with a dielectric material; and
etching back the spacer and the dielectric material adjacent to the spacer, and a remaining portion of the dielectric material forming a dielectric pillar, wherein the channel layer surrounds the dielectric pillar.

### Claim 14 (depends on 13)

The method for fabricating the memory device according to claim 13, further comprising:
forming a trench penetrating the laminated body, the trench exposing a portion of the substrate;
removing the sacrificial layer through the trench; and
sequentially forming the memory layer and the second conductive layer at the position where the sacrificial layer is removed.

### Claim 15 (depends on 14)

The method for fabricating the memory device according to claim 14, wherein a portion of the memory layer extends along the first direction and is disposed between the second conductive layer and the channel layer; other portions of the memory layer extend along a second direction and are disposed between the second conductive layer and the second insulating layer and between the second conductive layer and the third insulating layer, wherein the first direction and the second direction are intersected.

### Claim 16 (depends on 13)

The method for fabricating the memory device according to claim 13, further comprising:
forming a memory material layer extending on the laminated body and into the first opening after forming the first opening; and
removing an excessive portion of the memory material layer to form the memory layer disposed on a sidewall of the first opening.

### Claim 17 (depends on 16)

The method for fabricating the memory device according to claim 16, wherein the memory layer extends along the first direction and penetrates the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer.

### Claim 18 (depends on 13)

The method for fabricating the memory device according to claim 13, wherein the channel layer is disposed between the dielectric pillar and the memory layer.

### Claim 19 (depends on 13)

The method for fabricating the memory device according to claim 13, wherein the channel layer has an inner surface and an outer surface, the inner surface is opposite to the outer surface, wherein the inner surface contacts the dielectric pillar, and the outer surface contacts the memory layer.

### Claim 20 (depends on 11)

The method for fabricating the memory device according to claim 11 further comprising:
forming an oxide layer on a side surface of the first conductive layer exposed from the first opening through an oxidation process.