# US 2022/0285384 A1 · Protective liner layers in 3d memory structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285384 A1 - Document ID: US20220285384A1 - Status: Published application - Kind: A1 - Application number: 17/190,735 - Filed: 2021-03-03 - Published: 2022-09-08 - Earliest claimed: 2021-03-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Tsu Ching Yang; Sheng-Chih Lai; Yu-Wei Jiang; Kuo-Chang Chiang; Hung-Chang Sun; Chen-Jun Wu; Feng-Cheng Yang; Chung-Te Lin - Web page: https://patentgrep.com/patent/US20220285384A1 ## CPC - H10B 41/10: characterised by the top-view layout - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/10: characterised by the top-view layout - H10B 43/30: characterised by the memory core region - H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 51/30: characterised by the memory core region - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer. ## Claims ### Claim 1 A memory device comprising: a stack of gate electrode layers arranged over a substrate; interconnect dielectric layers arranged above and below each gate electrode layer; a first memory cell arranged over the substrate and comprising: a first source/drain conductive line extending vertically through the stack of gate electrode layers; a second source/drain conductive line extending vertically through the stack of gate electrode layers; a channel layer arranged on outermost sidewalls of and extending between the first and second source/drain conductive lines; a memory layer arranged on outermost sidewalls of the channel layer; a first barrier structure arranged between a first side of the first source/drain conductive line and a first side of the second source/drain conductive line; a first protective liner layer arranged directly between the first side of the first source/drain conductive line and the first barrier structure and arranged directly between the first side of the second source/drain conductive line and the first barrier structure; a second barrier structure on a second side of the first source/drain conductive line; and a second protective liner layer arranged directly between the second barrier structure and the second side of the first source/drain conductive line. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first protective liner layer is arranged along outermost sidewalls of the first and second source/drain conductive lines. ### Claim 3 (depends on 1) The memory device of claim 1, further comprising: a first dielectric layer arranged on outermost sidewalls of the first barrier structure. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the second protective liner layer continuously surrounds sidewalls of the second barrier structure. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the first protective liner layer comprises a metal or metal oxide. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the second protective liner layer comprises a metal or metal oxide. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the first protective liner layer comprises a different material than the first barrier structure, and wherein the second protective liner layer comprises a different material than the second barrier structure. ### Claim 8 (depends on 1) The memory device of claim 1, further comprising: a second memory cell comprising: a third source/drain conductive line extending vertically through the stack of gate electrode layers, wherein the third source/drain conductive line directly contacts the second protective liner layer and is spaced apart from the first source/drain conductive line by the second protective liner layer and the second barrier structure. ### Claim 9 A memory device comprising: a stack of gate electrode layers alternating with interconnect dielectric layers that are arranged over a substrate; a first source/drain conductive line and a second source/drain conductive line extending vertically through the stack of gate electrode layers; a channel layer and a memory layer extending between the first and second source/drain conductive lines; a first barrier structure extending vertically through the stack of gate electrode layers and arranged directly between the first and second source/drain conductive lines; a first protective liner layer arranged between the first barrier structure and the first source/drain conductive line, wherein the first protective liner layer is arranged on outer sidewalls and a lower surface of the first source/drain conductive line; and a second protective liner layer arranged on an upper surface of the first source/drain conductive line. ### Claim 10 (depends on 9) The memory device of claim 9, further comprising: a second barrier structure arranged over the second protective liner layer, wherein the second protective liner layer continuously surrounds outer sidewalls of the second barrier structure. ### Claim 11 (depends on 9) The memory device of claim 9, wherein a topmost surface of the first protective liner layer directly contacts a bottommost surface of the second protective liner layer. ### Claim 12 (depends on 9) The memory device of claim 9, further comprising: a dielectric layer arranged on outermost sidewalls of the first barrier structure and comprising a different material than the first barrier structure and the first protective liner layer. ### Claim 13 (depends on 9) The memory device of claim 9, further comprising: a third barrier structure arranged between the first barrier structure and the second source/drain conductive line, wherein a third protective liner layer is arranged on outer sidewalls and an upper surface of the second source/drain conductive line; and a fourth protective liner layer arranged on a lower surface of the second source/drain conductive line. ### Claim 14 (depends on 13) The memory device of claim 13, wherein the third protective liner layer comprises a same material as the first protective liner layer, and wherein the fourth protective liner layer comprises a same material as the second protective liner layer. ### Claim 15 (depends on 13) The memory device of claim 13, wherein the first protective liner layer is completely spaced apart from the third protective liner layer, and wherein the second protective liner layer is completely spaced apart from the fourth protective liner layer. ### Claim 16 (depends on 13) The memory device of claim 13, further comprising: a third barrier structure arranged below the fourth protective liner layer, wherein the fourth protective liner layer continuously surrounds outer sidewalls of the third barrier structure. ### Claim 17 A method comprising: forming a stack of dummy gate electrode layers arranged between interconnect dielectric layers over a substrate; forming a first trench within the stack of dummy gate electrode layers; replacing the dummy gate electrode layer with gate electrode layers; forming a memory layer, a channel layer, and a first dielectric layer within the first trench; filling remaining portions of the first trench with a dielectric material; forming first openings within the dielectric material to form first barrier structures within the first trench; forming a first protective liner material within the first openings; forming sacrificial structures within the first openings; removing portions of the first protective liner material and portions of the sacrificial structures to respectively form a first protective liner layer and second openings within the sacrificial structures; forming a second protective liner layer within the second openings of the sacrificial structures; forming second barrier structures within remaining portions of the second openings; and removing the sacrificial structures and replacing the sacrificial structures with a conductive material to form source/drain conductive lines surrounded by the first and second protective liner layers. ### Claim 18 (depends on 17) The method of claim 17, wherein the removing of the sacrificial structures comprises one or more etchants, and wherein the first and second protective liner layers have a slower rate of removal by the one or more etchants than the first and second barrier structures. ### Claim 19 (depends on 17) The method of claim 17, wherein the first protective liner layer comprises a different material than the first barrier structure, and wherein the second protective liner layer comprises a different material than the first barrier structure. ### Claim 20 (depends on 17) The method of claim 17, wherein the sacrificial structures comprise a different material than the first barrier structure and the second barrier structure.