# US 2022/0285367 A1 · Thin film transistor random access memory

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- Number: US 2022/0285367 A1
- Document ID: US20220285367A1
- Status: Published application
- Kind: A1
- Application number: 17/191,446
- Filed: 2021-03-03
- Published: 2022-09-08
- Earliest claimed: 2021-03-03
- Assignees: Micro Technology, Inc.
- Applicants: Micro Technology, Inc.
- Inventors: Richard E. Fackenthal
- Web page: https://patentgrep.com/patent/US20220285367A1

## CPC

- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- G11C 11/412: using field-effect transistors only
- H10B 10/18: {Peripheral circuit regions}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6728: {Vertical TFTs}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 20/43: Layouts of interconnections
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

## Claims

### Claim 1

An apparatus, comprising:
a memory cell comprising a plurality of transistors configured to store a logic state, the plurality of transistors comprising:
a first set of one or more transistors each comprising:
a respective first gate portion comprising a conductor formed above a substrate; and
a respective first channel portion comprising a pillar formed above the substrate and configured to be activated based at least in part on a voltage of the respective first gate portion; and
a second set of one or more transistors each comprising:
a respective second gate portion comprising a conductor formed above the substrate; and
a respective second channel portion comprising a doped portion of the substrate that is configured to be activated based at least in part on a voltage of the respective second gate portion.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the respective first channel portion of each transistor of the first set of one or more transistors comprises a plurality of pillars formed above the substrate.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the pillars of the first channel portions of all of the first set of one or more transistors have a common height dimension relative to the substrate.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the first set of one or more transistors comprises:
a first subset of transistors, wherein the pillar of the respective first channel portion of each transistor of the first subset has a first height dimension relative to the substrate; and
a second subset of transistors, wherein the pillar of the respective first channel portion of each transistor of the second subset has a second height dimension relative to the substrate.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein each transistor of the second set of one or more transistors is configured in a planar transistor arrangement.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein:
each transistor of the first set of one or more transistors is configured as an n-type transistor; and
each transistor of the second set of one or more transistors is configured as a p-type transistor.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein:
the first set of one or more transistors comprises four n-type transistors; and
the second set of one or more transistors comprises two p-type transistors.

### Claim 8

An apparatus, comprising:
a memory array comprising:
a first memory cell comprising a first plurality of transistors, the first plurality of transistors comprising a first plurality of pillars each formed above a substrate of the memory array and each configured to be activated by a respective gate conductor formed above the substrate of the memory array; and
a second memory cell comprising a second plurality of transistors, the second plurality of transistors comprising a second plurality of pillars each formed above the substrate of the memory array and each configured to be activated by a respective gate conductor formed above the substrate of the memory array.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein:
the first memory cell further comprises a third plurality of transistors each comprising a respective doped portion of the substrate that is configured to be activated by a respective gate conductor; and
the second memory cell further comprises a fourth plurality of transistors each comprising a respective doped portion of the substrate that is configured to be activated by a respective gate conductor.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein:
each transistor of the first plurality of transistors and each transistor of the second plurality of transistors is configured as an n-type transistor; and
each transistor of the third plurality of transistors and each transistor of the fourth plurality of transistors is configured as a p-type transistor.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein:
each transistor of the first plurality of transistors comprises a respective set of two or more of the first plurality of pillars; and
each transistor of the second plurality of transistors comprises a respective set of two or more of the second plurality of pillars.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein each pillar of the first plurality of pillars and each pillar of the second plurality of pillars has a common height relative to the substrate.

### Claim 13 (depends on 12)

The apparatus of claim 12, further comprising:
one or more pillars having the common height relative to the substrate and configured to not be activated by any gate conductor.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the first plurality of pillars and the second plurality of pillars each comprise:
a respective first subset of pillars having a first height dimension relative to the substrate; and
a respective second subset of pillars having a second height dimension relative to the substrate.

### Claim 15 (depends on 14)

The apparatus of claim 14, further comprising:
one or more first pillars having the first height dimension relative to the substrate and configured to not be activated by any gate conductor; and
one or more second pillars having the second height dimension relative to the substrate and configured to not be activated by any gate conductor.

### Claim 16

An apparatus, comprising:
a memory cell comprising:
a first transistor comprising a first gate portion coupled with a first access line and a first channel portion coupled between a second access line and a first node of the memory cell, the first channel portion comprising a first pillar formed over a substrate;
a second transistor comprising a second gate portion coupled with a second node of the memory cell and a second channel portion coupled between the first node and a third node of the memory cell, the second channel portion comprising a second pillar formed over the substrate;
a third transistor comprising a third gate portion coupled with the first node and a third channel portion coupled between the third node and the second node, the third channel portion comprising a third pillar formed over the substrate; and
a fourth transistor comprising a fourth gate portion coupled with the first access line and a fourth channel portion coupled between the second node and a third access line, the fourth channel portion comprising a fourth pillar formed over the substrate.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the memory cell further comprises:
a fifth transistor comprising a fifth gate portion coupled with the second node and a fifth channel portion coupled between the first node and a fourth node of the memory cell, the fifth channel portion comprising a first doped portion of the substrate; and
a sixth transistor comprising a sixth gate portion coupled with the first node and a sixth channel portion coupled between the second node and the fourth node, the sixth channel portion comprising a second doped portion of the substrate.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the third node is configured to be coupled with a ground voltage source and the fourth node is configured to be coupled with a positive voltage source.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein each of the fifth transistor and the sixth transistor is configured as a p-type transistor.

### Claim 20 (depends on 16)

The apparatus of claim 16, wherein:
the first channel portion comprises a plurality of first pillars;
the second channel portion comprises a plurality of second pillars;
the third channel portion comprises a plurality of third pillars; and
the fourth channel portion comprises a plurality of fourth pillars.

### Claim 21 (depends on 16)

The apparatus of claim 16, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor is configured as an n-type transistor.

### Claim 22 (depends on 16)

The apparatus of claim 16, wherein each of the first pillar, the second pillar, the third pillar, and the fourth pillar have a first height dimension relative to the substrate.

### Claim 23 (depends on 22)

The apparatus of claim 22, wherein each of the first gate portion, the second gate portion, the third gate portion, and the fourth gate portion comprise a respective conductor portion having a second height dimension relative to the substrate that is within the first height dimension.

### Claim 24 (depends on 22)

The apparatus of claim 22, wherein each of the first node and the second node comprises a respective conductor portion having a third height dimension relative to the substrate that is within the first height dimension.

### Claim 25 (depends on 22)

The apparatus of claim 22, wherein the first access line comprises a conductor portion having a fourth height dimension relative to the substrate that is within the first height dimension.

### Claim 26 (depends on 16)

The apparatus of claim 16, wherein each of the first pillar and the fourth pillar have a first height dimension relative to the substrate and each of the second pillar and the third pillar have a second height dimension relative to the substrate.

### Claim 27 (depends on 26)

The apparatus of claim 26, wherein:
the first node comprises a first conductive portion coupling the first pillar with the second pillar and having a third height dimension relative to the substrate that is between the first height dimension and the second height dimension; and
the second node comprises a second conductive portion coupling the third pillar with the fourth pillar and having a fourth height dimension relative to the substrate that is between the first height dimension and the second height dimension.

### Claim 28 (depends on 26)

The apparatus of claim 26, wherein the first access line comprises a conductor portion having a fifth height dimension relative to the substrate that is within the first height dimension.

### Claim 29

A method, comprising:
forming a memory cell comprising a plurality of transistors configured to store a logic state, wherein forming the memory cell comprises:
forming a first set of one or more transistors each comprising:
a respective gate portion comprising a conductor formed above a substrate; and
a respective channel portion comprising a pillar formed above the substrate and configured to be activated based at least in part on a voltage of the respective gate portion; and
forming a second set of one or more transistors each comprising:
a respective gate portion comprising a conductor formed above the substrate; and
a respective channel portion comprising a doped portion of the substrate that is configured to be activated based at least in part on a voltage of the respective gate portion.

### Claim 30

A method, comprising:
forming a memory cell of a memory array, wherein forming the memory cell comprises:
forming a first transistor comprising a first gate portion coupled with a first access line and a first channel portion coupled between a second access line and a first node of the memory cell, the first channel portion comprising a first pillar over a substrate of the memory array;
forming a second transistor comprising a second gate portion coupled with a second node of the memory cell and a second channel portion coupled between the first node and a third node of the memory cell, the second channel portion comprising a second pillar over the substrate;
forming a third transistor comprising a third gate portion coupled with the first node and a third channel portion coupled between the third node and the second node, the third channel portion comprising a third pillar over the substrate; and
forming a fourth transistor comprising a fourth gate portion coupled with the first access line and a fourth channel portion coupled between the second node and a third access line, the fourth channel portion comprising a fourth pillar over the substrate.