# US 2022/0285362 A1 · Methods and structures for three-dimensional dynamic random-access memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285362 A1 - Document ID: US20220285362A1 - Status: Published application - Kind: A1 - Application number: 17/674,353 - Filed: 2022-02-17 - Published: 2022-09-08 - Earliest claimed: 2021-03-05 - Assignees: Applied Materials, Inc. - Applicants: Applied Materials, Inc. - Inventors: Fredrick David FISHBURN; Arvind KUMAR; Sony VARGHESE; Chang Seok KANG; Sung-Kwan KANG; Tomohiko KITAJIMA - Web page: https://patentgrep.com/patent/US20220285362A1 ## CPC - H10B 12/05: {Making the transistor} - G11C 5/10: for interconnecting capacitors - H10B 12/03: {Making the capacitor or connections thereto} - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H10B 12/482: {Bit lines} - H10B 12/488: {Word lines} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features. ## Claims ### Claim 1 A method for forming a three-dimensional dynamic random-access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) material and crystalline silicon germanium (c-SiGe) material using an heteroepitaxy process onto a substrate; and etching of a pattern of holes with at least one high aspect ratio (HAR) hole into the substrate, the pattern of holes configured to provide chemistry access to the alternating layers of c-Si material and c-SiGe material to laterally etch or deposit materials to form 3D DRAM features of the 3D DRAM structure without subsequent HAR etching of holes in the substrate to form the 3D DRAM features. ### Claim 2 (depends on 1) The method of claim 1, further comprising: merging a portion of the pattern of holes formed by etching material between the portion of the pattern of holes to form an active area isolation slot of the 3D DRAM structure. ### Claim 3 (depends on 1) The method of claim 1, further comprising: depositing different materials in different holes to block or allow lateral or vertical recess process for 3D DRAM cell formation. ### Claim 4 (depends on 1) The method of claim 1, further comprising: forming an isolation slot which has a liner of a first dielectric material which is removable by exposure to hydrogen fluoride (HF) and which has ends filled with a second dielectric material impervious to HF, the isolation slot configured to provide lateral cell isolation and give structure support to the 3D DRAM structure. ### Claim 5 (depends on 4) The method of claim 4, further comprising: forming a lower electrode of a capacitor of the 3D DRAM structure that is supported at one or more ends of the isolation slot that are filled with the second dielectric material; and removing the liner of the first dielectric material of the isolation slot to provide space to fill with a high-k top electrode material for increased 3D DRAM cell capacitance of the 3D DRAM structure while maintaining structural support of the lower electrode. ### Claim 6 (depends on 1) The method of claim 1, further comprising: etching the pattern of holes using a mask and etching process that etches both c-Si material and c-SiGe material. ### Claim 7 (depends on 1) The method of claim 1, further comprising: selectively etching the c-SiGe material from inside the at least one HAR hole to form a lateral feature extending from a sidewall of the at least one HAR hole. ### Claim 8 (depends on 7) The method of claim 7, further comprising: selectively etching the c-Si material in the at least one HAR hole to increase a size of the at least one HAR hole and a height of the lateral feature; or etching the c-Si material and the c-SiGe material in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral feature, and a width of the later feature that extends into the c-SiGe material. ### Claim 9 A method for forming a three-dimensional dynamic random-access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) material and crystalline silicon germanium (c-SiGe) material using an heteroepitaxy process on a substrate; etching of a pattern of holes with at least one high aspect ratio (HAR) hole into the substrate, the pattern of holes configured to provide chemistry access to the alternating layers of c-Si material and c-SiGe material to laterally etch or deposit materials to form 3D DRAM features of the 3D DRAM structure without subsequent HAR etching of holes in the substrate to form the 3D DRAM features; merging a portion of the pattern of holes formed by etching material between the portion of the pattern of holes to form slot features of the 3D DRAM structure; forming an isolation slot from at least one slot feature which has a liner of a first dielectric material which is removable by exposure to hydrogen fluoride (HF) and which has ends filled with a second dielectric material impervious to HF, the isolation slot configured to provide lateral cell isolation and give structure support to the 3D DRAM structure; forming a lower electrode of a capacitor of the 3D DRAM structure that is supported at one or more ends of the isolation slot that are filled with the second dielectric material; and removing the liner of the first dielectric material of the isolation slot to provide space to fill with a high-k top electrode material for increased 3D DRAM cell capacitance while maintaining structural support of the lower electrode. ### Claim 10 (depends on 9) The method of claim 9, further comprising: etching a wordline hole between two isolation slots to form a wordline structure; selectively etching the c-SiGe material through a top opening of the wordline hole to form lateral wordline features extending to the two isolation slots; forming a source/drain and spacer of the 3D DRAM structure by extending the lateral wordline features until limited by the two isolation slots; depositing a conformal layer of doped oxide in the wordline hole; etching back the conformal layer of doped oxide to leave doped regions for a source/drain of the 3D DRAM structure; depositing a gate oxide layer in the wordline hole; and depositing a gate electrode to fill the wordline hole. ### Claim 11 (depends on 10) The method of claim 10, further comprising: anisotropically etching a slit between two wordline structures to form a bitline structure; selectively etching c-SiGe material laterally in the slit from a top opening of the slit; forming the bitline structure by chemically depositing and etching from the top opening of the slit; and forming a conductive shield layer in the bitline structure to reduce noise coupling between multiple bitlines. ### Claim 12 (depends on 9) The method of claim 9, further comprising: etching the pattern of holes using a mask and etching process that etches both c-Si material and c-SiGe material. ### Claim 13 (depends on 9) The method of claim 9, further comprising: selectively etching the c-SiGe material from inside the at least one HAR hole to form a lateral feature extending a sidewall of the at least one HAR hole. ### Claim 14 (depends on 13) The method of claim 13, further comprising: selectively etching the c-Si material in the at least one HAR hole to increase a size of the at least one HAR hole and a height of the lateral feature; or etching the c-Si material and the c-SiGe material in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral feature, and a width of the later feature that extends into the c-SiGe material. ### Claim 15 (depends on 9) The method of claim 9, further comprising: depositing different materials in different holes to block or allow lateral or vertical recess process for 3D DRAM cell formation. ### Claim 16 A structure for use in three-dimensional dynamic random-access memory (3D DRAM), comprising: at least one vertical wordline feature of the 3D DRAM formed via a high aspect ratio (HAR) central hole in a stack of alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe); and at least one horizontal bitline feature of the 3D DRAM adjacent perpendicular to the at least one vertical wordline feature of the 3D DRAM. ### Claim 17 (depends on 16) The structure of claim 16, wherein the at least one vertical wordline feature of the 3D DRAM has at least one gate all-around (GAA) transistor structure. ### Claim 18 (depends on 17) The structure of claim 17, wherein the at least one GAA transistor structure has lateral source/drain doping areas and spacers that are symmetrical to the HAR central hole and self-aligned. ### Claim 19 (depends on 16) The structure of claim 16, wherein the at least one horizontal bitline feature of the 3D DRAM has a shield configured to reduce noise coupling formed over the at least one horizontal bitline feature. ### Claim 20 (depends on 16) The structure of claim 16, wherein the at least one vertical wordline feature of the 3D DRAM is positioned between two isolation features that are configured to provide structural support for the 3D DRAM.