# US 2022/0285353 A1 · Semiconductor memory device

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- Number: US 2022/0285353 A1
- Document ID: US20220285353A1
- Status: Published application
- Kind: A1
- Application number: 17/491,971
- Filed: 2021-10-01
- Published: 2022-09-08
- Earliest claimed: 2021-03-05
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jin Sun CHO
- Web page: https://patentgrep.com/patent/US20220285353A1

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/05: {Making the transistor}
- H10B 12/482: {Bit lines}
- H10B 12/488: {Word lines}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/674: {characterised by the active materials}
- H10D 1/714: {having horizontal extensions}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor memory device includes: an active layer spaced apart from a substrate wherein the active layer extends in a direction parallel to the substrate, and includes a channel; a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer; a capacitor coupled to a second end of the active layer; and a double word line including a pair of dual work function electrodes that extend in a direction crossing the active layer with the active layer interposed therebetween, wherein each of the dual work function electrodes includes: a high work function electrode which is adjacent to the bit line; and a low work function electrode which is adjacent to the capacitor and having a lower work function than the high work function electrode.

## Claims

### Claim 1

A semiconductor memory device comprising:
an active layer spaced apart from a substrate wherein the active layer extends in a direction parallel to the substrate and includes a channel;
a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer;
a capacitor coupled to an end of a second end of the active layer; and
a double word line including a pair of dual work function electrodes extending in a direction crossing the active layer with the active layer interposed therebetween,
wherein each of the dual work function electrodes includes:
a high work function electrode which is adjacent to the bit line; and
a low work function electrode which is adjacent to the capacitor and having a lower work function than the high work function electrode.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the low work function electrode has a lower work function than a mid-gap work function of silicon, and
the high work function electrode has a higher work function than the mid-gap work function of silicon.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the low work function electrode includes an N-type doped polysilicon.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein the high work function electrode includes a metal-based material.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein the high work function electrode includes titanium nitride, tungsten, or a stack of titanium nitride and tungsten.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the high work function electrode has a larger volume than the low work function electrode.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, wherein each of the high work function electrode and the low work function electrode vertically overlaps with the active layer.

### Claim 8 (depends on 7)

The semiconductor memory device of claim 7, wherein an overlapping area between the high work function electrode and the active layer is larger than an overlapping area between the low work function electrode and the active layer.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, wherein the channel of the active layer includes
a thin-body channel which is thinner than the high work function electrode and the low work function electrode.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, wherein the active layer includes a semiconductor material or an oxide semiconductor material.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, wherein the active layer includes polysilicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide).

### Claim 12 (depends on 1)

The semiconductor memory device of claim 1, wherein the active layer further includes
a first source/drain region coupled to the bit line, and
a second source/drain region coupled to the capacitor.

### Claim 13 (depends on 12)

The semiconductor memory device of claim 12, further comprising:
a bit line side-ohmic contact between the bit line and the first source/drain region, and
a storage node side-ohmic contact between the capacitor and the second source/drain region.

### Claim 14 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a word line pad coupled to the double word line.

### Claim 15 (depends on 1)

The semiconductor memory device of claim 1, wherein the capacitor includes
a cylindrical storage node coupled to the end of the other side of the active layer.

### Claim 16

A semiconductor memory device, comprising:
a substrate;
active layers stacked in a direction perpendicular to a surface of the substrate and including channels;
a bit line coupled to first ends of the active layers and oriented in a direction perpendicular to the surface of the substrate;
capacitors coupled to second ends of the active layers and including storage nodes that are stacked in the direction perpendicular to the surface of the substrate; and
double word lines having a first word line and a second word line that are oriented in a direction parallel to the surface of the substrate with each of the active layers interposed therebetween,
wherein each of the first word line and the second word line includes:
a high work function electrode which is adjacent to the bit line; and
a low work function electrode which is adjacent to the storage nodes and having a lower work function than the high work function electrode.

### Claim 17 (depends on 16)

The semiconductor memory device of claim 16, wherein the low work function electrode has a lower work function than a mid-gap work function of silicon, and
the high work function electrode has a higher work function than the mid-gap work function of silicon.

### Claim 18 (depends on 16)

The semiconductor memory device of claim 16, wherein the low work function electrode includes N-type doped polysilicon, and
the high work function electrode includes a metal-based material.

### Claim 19 (depends on 16)

The semiconductor memory device of claim 16, wherein the high work function electrode includes titanium nitride, tungsten, or a stack of titanium nitride and tungsten.

### Claim 20 (depends on 16)

The semiconductor memory device of claim 16, wherein the channels of the active layers include
a thin-body channel which is thinner than the high work function electrode and the low work function electrode.

### Claim 21 (depends on 16)

The semiconductor memory device of claim 16, wherein the active layers include
a semiconductor material or an oxide semiconductor material.

### Claim 22 (depends on 16)

The semiconductor memory device of claim 16, wherein the active layers include polysilicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide).

### Claim 23 (depends on 16)

The semiconductor memory device of claim 16, wherein the active layer further includes
a first source/drain region coupled to the bit line, and
a second source/drain region coupled to the capacitor.

### Claim 24 (depends on 23)

The semiconductor memory device of claim 23, further comprising:
a bit line side-ohmic contact between the bit line and the first source/drain region, and
a storage node side-ohmic contact between the capacitor and the second source/drain region.

### Claim 25 (depends on 16)

The semiconductor memory device of claim 16, further comprising:
a word line pad coupled in common to the first word line and the second word line.

### Claim 26 (depends on 6)

The semiconductor memory device of claim 6, wherein each of the capacitors includes
a cylindrical storage node coupled to the ends of the other side of he active layers,
a dielectric layer over the storage node, and
a plate node over the dielectric layer.

### Claim 27 (depends on 16)

The semiconductor memory device of claim 16, wherein the substrate includes
a peripheral circuit portion suitable for controlling the memory cells.