# US 2022/0285342 A1 · Deep trench via for three-dimensional integrated circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0285342 A1
- Document ID: US20220285342A1
- Status: Published application
- Kind: A1
- Application number: 17/825,664
- Filed: 2022-05-26
- Published: 2022-09-08
- Earliest claimed: 2018-06-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Yih WANG; Rishabh MEHANDRU; Mauro J. KOBRINSKY; Tahir GHANI; Mark BOHR; Marni NABORS
- Web page: https://patentgrep.com/patent/US20220285342A1

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

## Claims

### Claim 1

A three-dimensional (3D) integrated circuit (IC) assembly comprising:
a first IC die that includes:
a logic layer including a transistor array with a plurality of logic transistors, wherein the plurality of logic transistors includes a plurality of fins of semiconductor material;
a first interconnect on a first side of the logic layer;
a second interconnect on a second side of the logic layer, wherein the second side is opposite the first side; and
a deep trench via in the logic layer to conductively couple the first interconnect with the second interconnect, wherein the second side is opposite the first side, and wherein the deep trench via extends through a diffusion region or a gate region of a dummy transistor of the transistor array; and
a second IC die coupled to a front side of the second IC die, wherein the second IC die is to communicate with another device via the first interconnect, the deep trench via, and the second interconnect.

### Claim 2 (depends on 1)

The 3D IC assembly of claim 1, wherein the dummy transistor is between individual logic transistors of the plurality of logic transistors.

### Claim 3 (depends on 1)

The 3D IC assembly of claim 1, wherein one or more fins of the plurality of fins are in the diffusion region, and wherein the deep trench via is around the one or more fins.

### Claim 4 (depends on 1)

The 3D IC assembly of claim 1, wherein the fins do not extend into the deep trench via.

### Claim 5 (depends on 1)

The 3D IC assembly of claim 1, wherein the deep trench via includes a first portion on a second portion, wherein the first portion has a greater width than a second portion in a direction that is transverse to a long axis of the plurality of fins.

### Claim 6 (depends on 1)

The 3D IC assembly of claim 1, further comprising a via to electrically couple the deep trench via to the first interconnect, wherein the via has a width that is less than a width of the deep trench via.

### Claim 7 (depends on 1)

The 3D IC assembly of claim 1, wherein the deep trench via extends across multiple fins of the plurality of fins.

### Claim 8 (depends on 1)

The 3D IC assembly of claim 1, further comprising a sidewall spacer between the deep trench via and an adjacent gate region or diffusion region.

### Claim 9 (depends on 8)

The 3D IC assembly of claim 8, wherein the conductive material is in the diffusion region of the dummy transistor, and wherein the sidewall spacer is between the diffusion region and the adjacent gate region.

### Claim 10 (depends on 9)

The 3D IC assembly of claim 9, wherein the adjacent gate region includes a gate stack of a logic transistor.

### Claim 11 (depends on 8)

The 3D IC assembly of claim 8, wherein the conductive material is in the gate region of the dummy transistor, and wherein the sidewall spacer is between the gate region and the adjacent diffusion region.

### Claim 12 (depends on 1)

The 3D IC assembly of claim 1, wherein a backside of the first die is coupled to a motherboard, and wherein the another device is coupled to the motherboard.

### Claim 13

An integrated circuit (IC) die comprising:
a logic layer including a transistor array with a plurality of fins of semiconductor material;
a deep trench via in the logic layer to electrically couple a first interconnect on a first side of the logic layer with a second interconnect on a second side of the logic layer, wherein the second side is opposite the first side, and wherein the deep trench via includes a conductive material in a diffusion region or a gate region of a dummy transistor of the transistor array; and
a sidewall spacer between the conductive material in the diffusion region or the gate region of the dummy transistor and an adjacent gate region or diffusion region.

### Claim 14 (depends on 13)

The IC die of claim 13, wherein the dummy transistor is between individual logic transistors in the logic layer.

### Claim 15 (depends on 13)

The IC die of claim 13, wherein one or more fins of the plurality of fins are in the diffusion region, and wherein the deep trench via is around the one or more fins.

### Claim 16 (depends on 13)

The IC die of claim 13, wherein the fins do not extend into the deep trench via.

### Claim 17 (depends on 13)

The IC die of claim 13, wherein the deep trench via includes a first portion on a second portion, wherein the first portion has a greater width than a second portion in a direction that is transverse to a long axis of the plurality of fins.

### Claim 18 (depends on 13)

The IC die of claim 13, further comprising a via to electrically couple the deep trench via to the first interconnect, wherein the via has a width that is less than a width of the deep trench via.

### Claim 19 (depends on 13)

The IC die of claim 13, wherein the conductive material is in the diffusion region of the dummy transistor, and wherein the sidewall spacer is between the diffusion region and the adjacent gate region.

### Claim 20 (depends on 13)

The IC die of claim 13, wherein the conductive material is in the gate region of the dummy transistor, and wherein the sidewall spacer is between the gate region and the adjacent diffusion region.

### Claim 21

A computer system comprising:
a circuit board;
a first integrated circuit (IC) die having a first side and a second side, wherein the first side is coupled to the circuit board, and wherein the first IC die includes:
a logic layer including a transistor array with a plurality of fins of semiconductor material to form a plurality of logic transistors;
a first interconnect toward the first side from the logic layer;
a second interconnect toward the second side from the logic layer; and
a deep trench via in the logic layer to electrically couple the first interconnect with the second interconnect, wherein the deep trench via is in a diffusion region or a gate region of a dummy transistor in the transistor array.
a second IC die coupled to the second side of the IC die, wherein the second IC die is conductively coupled to another device on the circuit board via the second interconnect, the deep trench via, and the first interconnect.

### Claim 22 (depends on 21)

The computer system of claim 21, wherein the first IC die further includes a sidewall spacer between the diffusion region and an adjacent gate region or between the gate region and an adjacent diffusion region.

### Claim 23 (depends on 21)

The computer system of claim 21, wherein the dummy transistor is between individual logic transistors of the plurality of logic transistors.

### Claim 24 (depends on 21)

The computer system of claim 21, wherein one or more fins of the plurality of fins are in the diffusion region or gate region, and wherein the deep trench via is around the one or more fins.

### Claim 25 (depends on 21)

The computer system of claim 21, further comprising one or more of an antenna, a display, a network adapter, or a memory device coupled to the IC die.