# US 2022/0285339 A1 · Electrostatic discharge circuits and methods for operating the same

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- Number: US 2022/0285339 A1
- Document ID: US20220285339A1
- Status: Published application
- Kind: A1
- Application number: 17/351,111
- Filed: 2021-06-17
- Published: 2022-09-08
- Earliest claimed: 2021-03-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Tzu-Heng Chang; Hsin-Yu Chen; Pin-Hsin Chang
- Web page: https://patentgrep.com/patent/US20220285339A1

## CPC

- H10D 89/811: {using FETs as protective elements}
- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.

## Claims

### Claim 1

A circuit comprising:
a first transistor including a drain, a source, a gate, and a bulk, the drain of the first transistor connected to a first terminal, the source of the first transistor connected to receive a first voltage, and the gate and the bulk of the first transistor connected to receive a second voltage lower than the first voltage, and;
a second transistor including a drain, a source, a gate, and a bulk, the source, the gate, and the bulk of the second transistor connected to receive the second voltage, and the drain of the second transistor connected to the first terminal,
wherein esponse to the first terminal reaching a trigger voltage, the first transistor is configured to be turned on.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein in response to the drain of the first transistor reaches the trigger voltage, the second transistor is configured to be turned on.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the first transistor is configured to be turned on prior to the second transistor.

### Claim 4 (depends on 2)

The circuit of claim 2, further comprising a power clamp module connected between the source of the first transistor and the source of the second transistor, wherein in response to the first transistor turning on, a first current flows from the source of the second transistor to the source of the first transistor through the power clamp module.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the first transistor is configured to be turned off when the circuit is in a normal operation mode.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the first transistor is configured to be turned on in response to an electrostatic discharge (ESD) PD mode strike occurring.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the first transistor includes a drain extended n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), and the second transistor includes a drain extended n-MOSFET.

### Claim 8 (depends on 3)

The circuit of claim 3, wherein the power clamp module includes a third transistor, a source of the third transistor is connected to receive the first voltage, and a bulk and a drain of the third transistor are connected to receive the second voltage.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the third transistor is a big field-effect transistor.

### Claim 10 (depends on 9)

The circuit of claim 9, further comprising a fourth transistor, a source connected to receive the first voltage, a drain and a bulk of the fourth transistor connected to receive the second voltage.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein the power clamp module includes a R-C inverter node connected to the gate of the fourth transistor.

### Claim 12

A semiconductor device, comprising:
a substrate of a first conductivity type;
a first doped region of a second conductivity type;
a first doped stripe of the second conductivity type;
a second doped stripe of the second conductivity type;
a third doped stripe of the second conductivity type, wherein the first doped stripe is between the first doped region and the third doped stripe; and
a fourth doped stripe of the second conductivity type, wherein the second doped stripe is between the first doped region and the fourth doped stripe,
wherein the first and fourth doped stripes are configured to receive a first voltage, the second and third doped stripes are configured to receive a second voltage lower than the first voltage, the first doped region is configured as a drain of a pull up snapback transistor and a drain of a pull down snapback transistor, and the first doped region is wider than the first, second, third, and fourth stripes.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein in response to the first doped region reaching a trigger voltage, the first doped region and the first doped stripe are conducted, and the first doped region and the fourth doped stripe are conducted.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further comprising:
a first polysilicon stripe between the first doped region and the first doped stripe;
a second polysilicon stripe between the first doped region and the second doped stripe;
a third polysilicon stripe between the first and third doped stripes; and
a fourth polysilicon stripe between the second and fourth doped stripes.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first, second, third, and fourth polysilicon stripe are configured to receive the second voltage.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the first and second polysilicon stripe are configured to receive the second voltage, and the third and fourth polysilicon stripe are connected to a R-C inverter node.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the third and fourth polysilicon stripe are a gate of an embedded n-type MOSFET.

### Claim 18

A method of operating a circuit, comprising:
in response to a first terminal reaching a first trigger voltage, turning on a first transistor connected between the first terminal and a first voltage;
in response to the first terminal reaching a second trigger voltage, turning on a second transistor connected between the first terminal and a second voltage, wherein the second trigger voltage is greater than the first voltage,
wherein the first transistor includes a drain extended n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), and the second transistor includes a drain extended n-MOSFET.

### Claim 19 (depends on 18)

The method of claim 18, further comprising, in response to the second transistor turning on, a first current flowing through a power clamp module.

### Claim 20 (depends on 19)

The method of claim 19, further comprising, in response to the second transistor turning on, a second current flowing through a third transistor, wherein a gate of the third transistor is connected to a R-C inverter node of the power clamp module.