# US 2022/0285338 A1 · High esd immunity field-effect device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285338 A1 - Document ID: US20220285338A1 - Status: Published application - Kind: A1 - Application number: 17/191,496 - Filed: 2021-03-03 - Published: 2022-09-08 - Earliest claimed: 2021-03-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Yu-Hung YEH - Web page: https://patentgrep.com/patent/US20220285338A1 ## CPC - H10D 89/811: {using FETs as protective elements} - H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H10D 89/911: {using passive elements as protective elements} - H10D 89/931: {characterised by the dispositions of the protective arrangements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail. ## Claims ### Claim 1 An apparatus comprising: a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL); a metal interconnect layer formed on top of the FEOL layer, wherein the metal interconnect layer comprises a plurality of interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate; a power delivery network (PDN) formed under the semiconductor substrate in a backside layer; and a through substrate resistive component formed between the FEOL layer and a B-BEOL layer, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact of the through substrate resistive component is connected, through the PDN, to a power supply rail. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the backside layer comprises of one or more metal interconnect levels that are separated by one or more dielectric layers. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the resistive component has a vertically tapered profile for achieving a predetermined resistance value. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first contact of the through substrate resistive component is connected to a drain terminal of the FET through an interconnect formed in the FEOL layer. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the power supply rail is coupled to a solder bump pad formed over a bottom surface of the B-BEOL layer. ### Claim 6 An electrostatic discharge (ESD) protection device comprising: a plurality of transistors formed on a semiconductor substrate during a front-end-of-line (FEOL) process; metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors; and through substrate resistive components connected to drain terminals of the plurality of transistors through the metal interconnects, wherein the through substrate resistive components are configured to clamp an ESD voltage during an ESD event. ### Claim 7 (depends on 6) The electrostatic discharge (ESD) protection device of claim 6, wherein the plurality of transistors are connected in series between a high power supply rail and a low power supply rail. ### Claim 8 (depends on 6) The electrostatic discharge (ESD) protection device of claim 6, wherein the metal interconnects comprises one or more metal interconnect levels that are separated by one or more dielectric layers. ### Claim 9 (depends on 6) The electrostatic discharge (ESD) protection device of claim 6, wherein the through substrate resistive component is electrically connected to a power supply rail through a power delivery network (PDN). ### Claim 10 (depends on 9) The electrostatic discharge (ESD) protection device of claim 9, wherein the through substrate resistive component is formed between an FEOL and a backside back-end-of-line (B-BEOL) layers that are formed during the FEOL process and a B-BEOL process, respectively. ### Claim 11 (depends on 10) The electrostatic discharge (ESD) protection device of claim 10, wherein the power supply rail is coupled to a solder bump pad formed over a bottom surface of the B-BEOL layer. ### Claim 12 (depends on 6) The electrostatic discharge (ESD) protection device of claim 6, wherein the resistive component has a vertically tapered profile for achieving a predetermined resistance value. ### Claim 13 (depends on 10) The electrostatic discharge (ESD) protection device of claim 10, wherein the PDN formed under the semiconductor substrate during the B-BEOL process. ### Claim 14 (depends on 6) The electrostatic discharge (ESD) protection device of claim 6, wherein a length and width of the through substrate resistive component is based on a predetermined resistance value. ### Claim 15 A method of forming an electrostatic discharge (ESD) protection device comprising: forming a field effect transistor on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process; forming a metal interconnect layer on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer is configured to interconnect the FET to a plurality of components formed on the semiconductor substrate; forming a power delivery network (PDN) under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process; and forming a through substrate resistive component between the FEOL layer and a B-BEOL layer, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and a second contact of the through substrate resistive component is connected, through the PDN, to a power supply rail. ### Claim 16 (depends on 15) The method of claim 15, further comprises: forming one or more metal interconnect levels in the backside layer that are separated by one or more dielectric layers. ### Claim 17 (depends on 15) The method of claim 15, further comprises: tapering the resistive component into a predetermined profile for achieving a predetermined resistance value. ### Claim 18 (depends on 15) The method of claim 15, further comprises: connecting, through an interconnect formed in the FEOL layer, the first contact of the through substrate resistive component to a drain terminal of the FET. ### Claim 19 (depends on 16) The method of claim 16, further comprises: coupling the power supply rail to solder bump pads formed over a bottom surface of the B-BEOL layer. ### Claim 20 (depends on 15) The method of claim 15, further comprises: determining a length and a width of the through substrate resistive component based on a predetermined resistance value.