# US 2022/0285334 A1 · Semiconductor Device and Method of Stacking Semiconductor Die for System-Level ESD Protection

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- Number: US 2022/0285334 A1
- Document ID: US20220285334A1
- Status: Published application
- Kind: A1
- Application number: 17/664,841
- Filed: 2022-05-24
- Published: 2022-09-08
- Earliest claimed: 2016-02-29
- Assignees: Semtech Corporation
- Applicants: Semtech Corporation
- Inventors: Changjun Huang; Jonathan Clark
- Web page: https://patentgrep.com/patent/US20220285334A1

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 90/811: {Multiple chips on leadframes}
- H10D 89/611: {using diodes as protective elements}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01257: {by reflowing}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07532: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/354: {comprising polymers}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 72/90: Bond pads, in general
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/014: {using batch processing}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/473: {containing a filler}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/732: {between stacked chips}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

## Claims

### Claim 1

A semiconductor device, comprising:
a leadframe;
a first semiconductor die comprising a first transient voltage suppression (TVS) diode disposed over the leadframe;
a second semiconductor die comprising a second TVS diode disposed over the first semiconductor die, wherein the first TVS diode and second TVS diode are coupled in parallel between a first terminal of the leadframe and a second terminal of the leadframe; and
an encapsulant deposited over the first semiconductor die, second semiconductor die, and leadframe, wherein the semiconductor device is configured to protect a separate semiconductor package from a transient electrical signal by routing the transient electrical signal through the first TVS diode and second TVS diode in parallel.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor die is bonded to the leadframe by a conductive bump.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor die is bonded to the second semiconductor die by a conductive bump.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor die is bonded to the second semiconductor die by thermocompression.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further including:
a conductive via formed in the first semiconductor die; and
a contact pad formed on the second semiconductor die and aligned with the conductive via.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device has exactly two terminals.

### Claim 7

A semiconductor device, comprising:
a first semiconductor die comprising a first discrete transient voltage suppression (TVS) diode;
a second semiconductor die comprising a second discrete TVS diode disposed over the first semiconductor die with the first discrete TVS diode and second discrete TVS diode electrically coupled in parallel; and
an encapsulant deposited over the first semiconductor die and second semiconductor die.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the semiconductor device has exactly two electrical terminals.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the semiconductor device is configured to protect a separate semiconductor package from a transient voltage.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, further including a third semiconductor die comprising a third discrete TVS diode disposed over the first semiconductor die and second semiconductor die with the third discrete TVS diode electrically coupled in parallel with the first discrete TVS diode and second discrete TVS diode.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, further including:
a first conductive via formed through the first semiconductor die; and
a second conductive via formed through the second semiconductor die over the first conductive via.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, further including a solder bump disposed between the first semiconductor die and second semiconductor die.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, wherein the first semiconductor die is thermocompression bonded to the second semiconductor die.

### Claim 14

A semiconductor device, comprising:
a first semiconductor die including a first transient voltage suppression (TVS) diode;
a second semiconductor die including a second TVS diode electrically coupled in parallel with the first TVS diode, wherein the semiconductor device is configured to protect a separate semiconductor package from an electrical transient.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further including a third semiconductor die disposed over the first semiconductor die and second semiconductor die, wherein the third semiconductor die includes a third TVS diode coupled in parallel with the first TVS diode and second TVS diode.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the semiconductor device has exactly two electrical terminals.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, further including a solder bump disposed between the first semiconductor die and second semiconductor die.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the first semiconductor die is thermocompression bonded to the second semiconductor die.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, further including a substrate, wherein the second semiconductor die is coupled to the substrate through a conductive via of the first semiconductor die.

### Claim 20

A semiconductor device, comprising:
a first transient voltage suppression (TVS) diode; and
a second TVS diode coupled in parallel with the first TVS diode, wherein the semiconductor device is configured to protect a separate semiconductor package from a transient electrical signal.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, further including a third TVS diode coupled in parallel with the first TVS diode and second TVS diode.

### Claim 22 (depends on 20)

The semiconductor device of claim 20, further including an encapsulant deposited over the first semiconductor die, second semiconductor die, and leadframe.

### Claim 23 (depends on 20)

The semiconductor device of claim 20, further including:
a first conductive via formed through the first TVS diode; and
a second conductive via formed through the second TVS diode, wherein the first conductive via and second conductive via are aligned with each other and electrically coupled to each other.

### Claim 24 (depends on 20)

The semiconductor device of claim 20, further including a solder bump disposed between the first TVS diode and second TVS diode.

### Claim 25 (depends on 20)

The semiconductor device of claim 20, wherein the first TVS diode is thermocompression bonded to the second TVS diode.