# US 2022/0285331 A1 · Package structure and manufacturing method thereof

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- Number: US 2022/0285331 A1
- Document ID: US20220285331A1
- Status: Published application
- Kind: A1
- Application number: 17/192,816
- Filed: 2021-03-04
- Published: 2022-09-08
- Earliest claimed: 2021-03-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chuei-Tang Wang; Chung-Hao Tsai; Chen-Hua Yu; Tzu-Chun Tang
- Web page: https://patentgrep.com/patent/US20220285331A1

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}
- H01Q 9/0407: {Substantially flat resonant element parallel to ground plane, e.g. patch antenna (dipole H01Q9/285; monopole H01Q9/40)}
- H01Q 9/16: with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole (H01Q9/44 takes precedence)
- H01Q 21/065: {Patch antenna array}
- H01Q 21/067: {using endfire radiating aerial units transverse to the plane of the array}
- H01Q 21/24: Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction {(circularly polarised patch antennas H01Q9/0428; circularly polarised horns H01Q13/0241; cross-polarised horns H01Q13/0258; polarisation converters H01Q15/242; cross-polarised rear feeds H01Q19/136; crossed polarisation dual antenna H01Q25/001)}
- H01Q 21/28: Combinations of substantially independent non-interacting antenna units or systems {(multiple beam H01Q25/00)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H01Q 21/061: {Two dimensional planar arrays}
- H01Q 21/08: the units being spaced along or adjacent to a rectilinear path {(waveguide fed H01Q21/0037)}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 44/248: {for antennas}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a semiconductor die, an antenna substrate structure, and a redistribution layer. The semiconductor die is laterally wrapped by a first encapsulant. The antenna substrate structure is disposed over the semiconductor die, wherein the antenna substrate structure includes a circuit substrate and at least one antenna element inlaid in the circuit substrate. The redistribution layer is disposed between the semiconductor die and the antenna substrate structure, wherein the at least one antenna element is electrically connected with the semiconductor die through the circuit substrate and the redistribution layer. The at least one antenna element includes patch antennas.

## Claims

### Claim 1

A package structure, comprising:
a semiconductor die laterally wrapped by a first encapsulant;
an antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a circuit substrate and at least one antenna element inlaid in the circuit substrate; and
a redistribution layer disposed between the semiconductor die and the antenna substrate structure, wherein the at least one antenna element is electrically connected with the semiconductor die through the circuit substrate and the redistribution layer;
wherein the at least one antenna element includes patch antennas.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the semiconductor die includes a radio frequency integrated circuit.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the antenna substrate structure is laterally wrapped by a second encapsulant.

### Claim 4 (depends on 3)

The package structure of claim 3, further comprising a die attach film covering a surface of the at least one antenna element and a surface of the second encapsulant.

### Claim 5 (depends on 3)

The package structure of claim 3, wherein the first encapsulant is separate from the second encapsulant by the redistribution layer.

### Claim 6 (depends on 3)

The package structure of claim 3, wherein the circuit substrate includes a core layer and metallization patterns disposed on the core layer, locations of the metallization patterns correspond to locations of the patch antennas, and a material of the second encapsulant is different from a material of the core layer.

### Claim 7 (depends on 1)

The package structure of claim 1, further comprising at least one dipole antenna disposed aside the semiconductor die and wrapped by the first encapsulant, wherein a polarization of electromagnetic waves emitted by the at least one dipole antenna is perpendicular to a polarization of electromagnetic waves emitted by the patch antennas.

### Claim 8 (depends on 7)

The package structure of claim 7, further comprising conductive vias located aside of the semiconductor die and located between the semiconductor die and the at least one dipole antenna.

### Claim 9 (depends on 1)

The package structure of claim 1, further comprising at least one dipole antenna embedded in the circuit substrate and located beside the at least one antenna element, wherein a polarization of electromagnetic waves emitted by the at least one dipole antenna is perpendicular to a polarization of the electromagnetic waves emitted by the patch antennas.

### Claim 10 (depends on 9)

The package structure of claim 9, further comprising conductive vias located aside of the semiconductor die and wrapped by the first encapsulant.

### Claim 11 (depends on 1)

The package structure of claim 1, further comprising at least one integrated passive device electrically connected to the semiconductor die.

### Claim 12

A package structure, comprising:
a redistribution layer having a first surface and a second surface opposite to the first surface;
an antenna substrate structure, disposed over the first surface of the redistribution layer and laterally wrapped by a first encapsulant, wherein the antenna substrate structure includes a first laminated layer, a core layer disposed on the first laminated layer, a second laminated layer disposed on the core layer, and the first laminated layer includes at least one antenna element;
at least one integrated passive device, disposed over the second surface of the redistribution layer and encapsulated by a second encapsulant;
a first semiconductor die and a second semiconductor die, disposed over the second surface of the redistribution layer and located between the at least one integrated passive device and the antenna substrate structure; and
a connector, disposed over the second surface of the redistribution layer and located aside of the at least one integrated passive device,
wherein a span of the second encapsulant is smaller than a span of the first encapsulant, the connector is located outside of the second encapsulant, and a portion of the second surface of the redistribution layer is exposed.

### Claim 13 (depends on 12)

The package structure of claim 12, further comprising a metal shielding covering a top surface and sidewalls of the second encapsulant, wherein the metal shielding is connected to the second surface of the redistribution layer.

### Claim 14 (depends on 12)

The package structure of claim 12, wherein the at least one antenna element includes patch antennas.

### Claim 15 (depends on 12)

The package structure of claim 12, wherein the first semiconductor die is a radio frequency integrated circuit or a power management integrated circuit and the second semiconductor die is the other.

### Claim 16 (depends on 12)

The package structure of claim 12, wherein the first semiconductor die, the second semiconductor die, and the at least one integrated passive device are encapsulated by the second encapsulant.

### Claim 17 (depends on 12)

The package structure of claim 12, further comprising a third encapsulant laterally wrapping the first and second semiconductor dies.

### Claim 18

A method for forming a package structure, comprising:
providing an antenna substrate structure having a circuit substrate and at least one antenna element inlaid in the circuit substrate;
disposing the antenna substrate structure over a carrier, facing the at least one antenna element toward the carrier;
molding the antenna substrate structure with a first encapsulant covering sidewalls of the antenna substrate structure;
forming a redistribution layer on the molded antenna substrate structure and the first encapsulant;
disposing a semiconductor die on the redistribution layer; and
molding the semiconductor die with a second encapsulant,
wherein the at least one antenna element is electrically coupled with the semiconductor die through the circuit substrate and the redistribution layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
forming at least one dipole antenna aside the semiconductor die and wrapping by the second encapsulant,
wherein a polarization of electromagnetic waves emitted by the at least one dipole antenna is perpendicular to a polarization of electromagnetic waves emitted by the at least one antenna element.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
forming at least one dipole antenna embedded in the circuit substrate and located beside the at least one antenna element,
wherein a polarization of electromagnetic waves emitted by the at least one dipole antenna is perpendicular to a polarization of electromagnetic waves emitted by the at least one antenna element.