# US 2022/0285318 A1 · Semiconductor packages and methods for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285318 A1 - Document ID: US20220285318A1 - Status: Published application - Kind: A1 - Application number: 17/382,916 - Filed: 2021-07-22 - Published: 2022-09-08 - Earliest claimed: 2021-03-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Shin-Yi YANG; Ming-Han LEE; Shau-Lin SHUE - Web page: https://patentgrep.com/patent/US20220285318A1 ## CPC - H10W 90/00: Package configurations - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/69: Insulating materials thereof - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/01: Manufacture or treatment - H10W 74/10: characterised by their shape or disposition - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/635: {Through-vias} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 74/147: {the encapsulations being multilayered} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging. ## Claims ### Claim 1 A semiconductor package, comprising: a first integrated circuit die having a first cutting surface, wherein the first integrated circuit die comprises a first edge interconnect feature extending to the first cutting surface; a second integrated circuit die having a second cutting surface, wherein the second integrated circuit die comprises a second edge interconnect feature extending to the second cutting surface; and an inter-chip connector having a first end contacting the first edge interconnect feature and a second end contacting the second edge interconnect feature. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first integrated circuit die further comprises a first interconnect structure, and the first edge interconnect feature is connected to the first interconnect structure. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the first interconnect structure comprises: an IMD (inter metal dielectric) layer; and a conductive feature embedded in the IMD layer, wherein an inner end of the first edge interconnect feature is connected to the conductive feature, and an outer end of the first edge interconnect feature extends to the first cutting surface of the first interconnect feature. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the first interconnect structure further comprises a sealing ring, and the first edge interconnect feature extends through an opening in the sealing ring. ### Claim 5 (depends on 4) The semiconductor package of claim 4, further comprising an encapsulant layer formed between the first integrated circuit die and the second integrated circuit die, and wherein the inter-chip connector is formed in the encapsulant layer. ### Claim 6 (depends on 3) The semiconductor package of claim 3, wherein the first integrated circuit die further comprises a plurality of external contacts formed on the first interconnect structure. ### Claim 7 (depends on 6) The semiconductor package of claim 6, further comprising an interposer substrate attached to the plurality of external contacts of the first integrated circuit die. ### Claim 8 A semiconductor package, comprising: a substrate; a first integrated circuit die attached to the substrate, wherein the first integrated circuit die has a first cutting surface; a second integrated circuit die attached to the substrate adjacent the first integrated circuit die, wherein the second integrated circuit die has a second cutting surface, and the first cutting surface faces the second cutting surface; and a plurality of inter-chip connectors formed between the first integrated circuit die and second integrated circuit die, wherein a first end of each of the inter-chip connector contacts the first cutting surface and a second end of the inter-chip connector contacts the second cutting surface. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the substrate is an interposer substrate, and the first integrated circuit die connected to the interposer substrate through a plurality of first external contacts. ### Claim 10 (depends on 9) The semiconductor package of claim 9, further comprising an encapsulant layer, wherein the plurality of inter-chip connectors are embedded in the encapsulant layer. ### Claim 11 (depends on 8) The semiconductor package of claim 8, wherein the first integrated circuit die comprises: one or more transistors; an interconnect structure comprising two or more IMD layers formed over the one or more transistors; and a plurality of edge interconnect features, wherein each of the plurality of edge interconnect feature has an inner end embedded in one of the two or more IMD layers and an outer end in contact with one of the plurality of the inter-chip connectors. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the interconnect structure comprises a sealing ring formed in the two or more IMD layers, and the plurality of edge interconnect features extend through openings in the sealing ring. ### Claim 13 (depends on 11) The semiconductor package of claim 11, wherein the first integrated circuit die has four cutting surfaces including the first cutting surface, and the plurality of edge interconnect features are symmetrically distributed along all of the four cutting surfaces of the first integrated circuit die. ### Claim 14 (depends on 13) The semiconductor package of claim 13, further comprises a plurality of conductive bumping features in contact with the plurality of edge interconnect features on all of the four cutting surfaces of the first integrated circuit die. ### Claim 15 A method for forming a semiconductor device, comprising: forming a first integrated circuit die having a first edge interconnect feature, and a second integrated circuit die having a second edge interconnect feature, wherein the first edge interconnect feature is exposed on a cutting surface of the first integrated circuit die, and the second edge interconnect feature is exposed on a cutting surface of the second integrated circuit die; positioning the first and second integrated circuit dies adjacent to each other such that the first edge conductive feature faces the second edge conductive feature; and forming an inter-chip connector between the first edge conductive feature and the second edge conductive feature. ### Claim 16 (depends on 15) The method of claim 15, wherein forming the inter-chip connector comprises performing a selective deposition. ### Claim 17 (depends on 16) The method of claim 16, wherein the selective deposition is performed by an electroless deposition process. ### Claim 18 (depends on 16) The method of claim 16, wherein the selective deposition is performed by an ALD or CVD process. ### Claim 19 (depends on 15) The method of claim 15, wherein forming the first integrated circuit die comprises: forming a device layer including one or more semiconductor devices; and forming an IMD layer over the device layer, wherein the IMD layer includes the first edge interconnect feature. ### Claim 20 (depends on 19) The method of claim 19, where forming the first integrated circuit die further comprises: forming a sealing ring in the IMD layer adjacent a perimeter of the first integrated circuit die, wherein the sealing ring has an opening, and the first edge interconnect feature extends through the opening.