# US 2022/0285307 A1 · Semiconductor Device, Semiconductor Arrangement and Method for Producing the Same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0285307 A1
- Document ID: US20220285307A1
- Status: Published application
- Kind: A1
- Application number: 17/687,797
- Filed: 2022-03-07
- Published: 2022-09-08
- Earliest claimed: 2021-03-08
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Paul Frank; Thomas Heinelt; Oliver Schilling; Sven Schmidbauer; Frank Wagner
- Web page: https://patentgrep.com/patent/US20220285307A1

## CPC

- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/073: {of die-attach connectors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 72/013: {of die-attach connectors}
- H10W 72/019: {of bond pads}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07355: {changes in materials}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/3528: {Intermetallic compounds}
- H10W 72/354: {comprising polymers}
- H10W 72/534: {being rectangular}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/764: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor wafer or a single semiconductor chip or die; and
a layer stack, wherein
the layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first layer comprises a content of Si of between 1 and 10%.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second layer comprises a content of V of between 1 and 10%.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first layer has a thickness in the range of 100 nm to 1000 nm.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second layer has a thickness of between 100 nm and 500 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a chip pad or metal contact layer arranged on a bottom surface of the semiconductor wafer, chip or die, wherein the layer stack is disposed on and electrically connected to the metal contact layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a front side metallization layer arranged on a top surface of the semiconductor wafer, chip or die, wherein the top surface of the semiconductor wafer, chip or die is a surface opposite the bottom surface and facing away from the layer stack.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a third layer, wherein the third layer is arranged between the second layer and the semiconductor wafer, chip or die.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the third layer has a thickness of between 100 nm and 1000 nm.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the third layer comprises Ti, WTi, Ta or an alloy comprising at least one of these materials.

### Claim 11 (depends on 1)

A semiconductor arrangement comprising:
a semiconductor device of claim 1;
an electrically conductive layer; and
an electrically conductive connection layer arranged between and electrically and mechanically coupling the semiconductor device to the electrically conductive layer.

### Claim 12 (depends on 11)

The semiconductor arrangement of claim 11, wherein the electrically conductive connection layer is a solder layer.

### Claim 13

A method comprising:
forming a layer stack on a semiconductor wafer or a single semiconductor chip or die, wherein forming the layer stack comprises
forming a second layer comprising NiV on the single semiconductor chip or die, and
forming a first layer comprising NiSi on the second layer such that the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

### Claim 14 (depends on 13)

The method of claim 13, further comprising
forming an electrically conductive connection layer on an electrically conductive layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising
arranging the semiconductor device on the electrically conductive connection layer, and
forming a permanent electrical and mechanical connection between the semiconductor device and the electrically conductive layer by means of the electrically conductive connection layer.