# US 2022/0285306 A1 · Rounded metal trace corner for stress reduction

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0285306 A1
- Document ID: US20220285306A1
- Status: Published application
- Kind: A1
- Application number: 17/825,739
- Filed: 2022-05-26
- Published: 2022-09-08
- Earliest claimed: 2019-01-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Dae-Woo KIM; Ajay JAIN; Neha M. PATEL; Rodrick J. HENDRICKS; Sujit SHARAN
- Web page: https://patentgrep.com/patent/US20220285306A1

## CPC

- H10W 70/685: comprising multiple insulating layers
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 90/00: Package configurations
- H10W 70/63: Vias, e.g. via plugs
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

## Claims

### Claim 1

A multi-die IC package, comprising:
a substrate;
an interconnect bridge embedded in the substrate, the interconnect bridge comprising:
a layer comprising oxygen; and
a metal trace in the layer comprising oxygen, the metal trace having a non-flat bottom surface, and the metal trace comprising a conductive material; and
a first die electrically coupled to the interconnect bridge and to the substrate; and
a second die electrically coupled to the interconnect bridge and to the substrate.

### Claim 2 (depends on 1)

The multi-die IC package of claim 1, further comprising:
a second metal trace, the second metal trace below the metal trace.

### Claim 3 (depends on 1)

The multi-die IC package of claim 1, wherein the interconnect bridge has a thickness of less than 100 microns.

### Claim 4 (depends on 3)

The multi-die IC package of claim 3, wherein the interconnect bridge has a thickness of less than 50 microns.

### Claim 5 (depends on 1)

The multi-die IC package of claim 1, wherein the metal trace electrically couples the first die to the second die.

### Claim 6 (depends on 1)

The multi-die IC package of claim 1, wherein the metal trace further comprises rounded corners.

### Claim 7 (depends on 1)

The multi-die IC package of claim 1, wherein the interconnect bridge is further covered by the substrate.

### Claim 8 (depends on 1)

The multi-die IC package of claim 1, wherein the first die and the second die are connected to the substrate through a surface mount technology.

### Claim 9 (depends on 1)

The multi-die IC package of claim 1, wherein the interconnect bridge allows communication between the first die and the second circuit die.

### Claim 10 (depends on 1)

The multi-die IC package of claim 1, wherein the substrate is an organic substrate.

### Claim 11

A multi-die IC package, comprising:
a substrate;
an interconnect bridge embedded in the substrate, the interconnect bridge comprising:
a layer comprising oxygen;
a groove in the layer comprising oxygen, the groove having a non-flat bottom surface; and
a metal trace in the groove, the metal trace comprising a conductive material; and
a first die electrically coupled to the interconnect bridge and to the substrate; and
a second die electrically coupled to the interconnect bridge and to the substrate.

### Claim 12 (depends on 11)

The multi-die IC package of claim 11, further comprising:
a second groove, the second groove trace below the groove; and
a second metal trace in the second groove, the second metal trace comprising the conductive material.

### Claim 13 (depends on 11)

The multi-die IC package of claim 11, wherein the interconnect bridge has a thickness of less than 100 microns.

### Claim 14 (depends on 13)

The multi-die IC package of claim 13, wherein the interconnect bridge has a thickness of less than 50 microns.

### Claim 15 (depends on 11)

The multi-die IC package of claim 11, wherein the metal trace electrically couples the first die to the second die.

### Claim 16 (depends on 11)

The multi-die IC package of claim 11, wherein the groove further comprises rounded corners.

### Claim 17 (depends on 11)

The multi-die IC package of claim 11, wherein the interconnect bridge is further covered by the substrate.

### Claim 18 (depends on 11)

The multi-die IC package of claim 11, wherein the first die and the second die are connected to the substrate through a surface mount technology.

### Claim 19 (depends on 11)

The multi-die IC package of claim 11, wherein the interconnect bridge allows communication between the first die and the second circuit die.

### Claim 20 (depends on 11)

The multi-die IC package of claim 11, wherein the substrate is an organic substrate.